ZHCSN08D August 2020 – April 2024 DRV8714-Q1 , DRV8718-Q1
PRODMIX
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 External Components
- 7.3.2 Device Interface Variants
- 7.3.3 Input PWM Control Modes
- 7.3.4 Smart Gate Driver
- 7.3.5 Tripler (Dual-Stage) Charge Pump
- 7.3.6 Wide Common-Mode Current Shunt Amplifiers
- 7.3.7 Pin Diagrams
- 7.3.8
Protection and Diagnostics
- 7.3.8.1 Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
- 7.3.8.2 Low IQ Powered Off Braking (POB, BRAKE)
- 7.3.8.3 Fault Reset (CLR_FLT)
- 7.3.8.4 DVDD Logic Supply Power on Reset (DVDD_POR)
- 7.3.8.5 PVDD Supply Undervoltage Monitor (PVDD_UV)
- 7.3.8.6 PVDD Supply Overvoltage Monitor (PVDD_OV)
- 7.3.8.7 VCP Charge Pump Undervoltage Lockout (VCP_UV)
- 7.3.8.8 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 7.3.8.9 Gate Driver Fault (VGS_GDF)
- 7.3.8.10 Thermal Warning (OTW)
- 7.3.8.11 Thermal Shutdown (OTSD)
- 7.3.8.12 Offline Short Circuit and Open Load Detection (OOL and OSC)
- 7.3.8.13 Watchdog Timer
- 7.3.8.14 Fault Detection and Response Summary Table
- 7.4 Device Functional Modes
- 7.5 Programming
- 8 Register Maps
- 9 Application Implementation
- 10Device Documentation and Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.3.7.1 Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
Figure 7-22 Input
Pin Structure
Figure 7-23 Input
Pin Structure (nSCS)