ZHCSI91B November 2017 – July 2018 DRV8304
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
請參考 PDF 數據表獲取器件具體的封裝圖。
The gate drive HS register is shown in Figure 41 and described in Table 15.
Register access type: Read/Write
| 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LOCK | Reserved | IDRIVEP_HS | Reserved | IDRIVEN_HS | ||||||
| R/W-011b | R/W-0b | R/W-111b | R/W-0b | R/W-111b | ||||||
| Bit | Field | Type | Default | Description |
|---|---|---|---|---|
| 10-8 | LOCK | R/W | 011b |
Write 110b to lock the settings by ignoring further register writes except to these bits and address 0x02h bits 0-2.
|
| 7 | Reserved | R/W | 0b |
Reserved |
| 6-4 | IDRIVEP_HS | R/W | 111b |
000b = 15 mA 001b = 15 mA 010b = 45 mA 011b = 60 mA 100b = 90 mA 101b = 105 mA 110b = 135 mA 111b = 150 mA |
| 3 | Reserved | R/W | 0b |
Reserved |
| 2-0 | IDRIVEN_HS | R/W | 111b |
000b = 30 mA 001b = 30 mA 010b = 90 mA 011b = 120 mA 100b = 180 mA 101b = 210 mA 110b = 270 mA 111b = 300 mA |