ZHCSI91B November 2017 – July 2018 DRV8304
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
請參考 PDF 數據表獲取器件具體的封裝圖。
| PIN | TYPE(1) | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| DRV8304H | DRV8304S | |||
| AGND | 32 | 32 | PWR | Device analog ground. Connect to system ground. |
| CAL | 31 | 31 | I | Amplifier calibration input. Set logic high to internally short amplifier inputs and perform offset calibration. |
| CPH | 2 | 2 | PWR | Charge pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic capacitor between the CPH and CPL pins. |
| CPL | 1 | 1 | PWR | Charge pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic capacitor between the CPH and CPL pins. |
| DVDD | 33 | 33 | PWR | 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally. |
| ENABLE | 30 | 30 | I | Gate driver enable. When this pin is logic low the device enters a low power sleep mode. An 5 to 32-µs low pulse can be used to reset fault conditions. |
| GAIN | 29 | — | I | Amplifier gain setting. The pin is a 4 level input pin set by an external resistor. |
| GHA | 6 | 6 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. |
| GHB | 15 | 15 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. |
| GHC | 16 | 16 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. |
| GLA | 8 | 8 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. |
| GLB | 13 | 13 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. |
| GLC | 18 | 18 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. |
| IDRIVE | 27 | — | I | Gate drive output current setting. This pin is a 7 level input pin set by an external resistor. |
| INHA | 34 | 34 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver (GHA). |
| INHB | 36 | 36 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver (GHB). |
| INHC | 38 | 38 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver (GHC). |
| INLA | 35 | 35 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver (GLA). |
| INLB | 37 | 37 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver (GLB). |
| INLC | 39 | 39 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver (GLC). |
| MODE | 26 | — | I | PWM input mode setting. This pin is a 4 level input pin set by an external resistor. |
| nFAULT | 25 | 25 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. |
| nSCS | — | 29 | I | Serial chip select. A logic low on this pin enables serial interface communication. |
| PGND | 40 | 40 | PWR | Device power ground. Connect to system ground. |
| SCLK | — | 28 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. |
| SDI | — | 27 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. |
| SDO | — | 26 | OD | Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor. |
| SHA | 7 | 7 | I | High-side source sense input. Connect to the high-side power MOSFET source. |
| SHB | 14 | 14 | I | High-side source sense input. Connect to the high-side power MOSFET source. |
| SHC | 17 | 17 | I | High-side source sense input. Connect to the high-side power MOSFET source. |
| SNA | 10 | 10 | I | Shunt amplifier input. Connect to the low-side of the current shunt resistor. |
| SNB | 11 | 11 | I | Shunt amplifier input. Connect to the low-side of the current shunt resistor. |
| SNC | 20 | 20 | I | Shunt amplifier input. Connect to the low-side of the current shunt resistor. |
| SOA | 23 | 23 | O | Shunt amplifier output. |
| SOB | 22 | 22 | O | Shunt amplifier output. |
| SOC | 21 | 21 | O | Shunt amplifier output. |
| SPA | 9 | 9 | I | Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. |
| SPB | 12 | 12 | I | Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. |
| SPC | 19 | 19 | I | Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. |
| VCP | 3 | 3 | PWR | Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins. |
| VDRAIN | 5 | 5 | I | High-side MOSFET drain sense input. Connect to the common point of the external MOSFET drains. |
| VDS | 28 | — | I | VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor. |
| VM | 4 | 4 | PWR | Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater than or equal to 10-uF local capacitance between the VM and PGND pins. |
| VREF | 24 | 24 | PWR | Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-μF, 6.3-V ceramic capacitor between the VREF and AGND pins. |