ZHCSI91B November 2017 – July 2018 DRV8304
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 3-Phase Smart Gate Drivers
- 7.3.2 DVDD Linear Voltage Regulator
- 7.3.3 Pin Diagrams
- 7.3.4 Low-Side Current-Shunt Amplifiers
- 7.3.5 Gate-Driver Protection Circuits
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- Table 1. DRV8304S Register Map
- 7.6.1 Status Registers (DRV8304S Only)
- 7.6.2
Control Registers (DRV8304S Only)
- 7.6.2.1 Driver Control Register (Address = 0x02) [reset = 0x00]
- 7.6.2.2 Gate Drive HS Register (Address = 0x03) [reset = 0x377]
- 7.6.2.3 Gate Drive LS Register (Address = 0x04) [reset = 0x777]
- 7.6.2.4 OCP Control Register (Address = 0x05) [reset = 0x145]
- 7.6.2.5 CSA Control Register (Address = 0x06) [reset = 0x283]
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
請參考 PDF 數據表獲取器件具體的封裝圖。
機械數據 (封裝 | 引腳)
- RHA|40
散熱焊盤機械數據 (封裝 | 引腳)
- RHA|40
訂購信息
7.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
The TDRIVE component is an integrated gate-drive state machine that provides automatic dead-time insertion through switching handshaking, parasitic dV/dt gate turnon prevention, and MOSFET gate-fault detection.
The first component of the TDRIVE state machine is automatic dead-time insertion. Dead time is the period of time between the switching of the external high-side and low-side MOSFETs to ensure that they do not cross conduct and cause shoot-through. The DRV8304 device uses the VGS voltage monitors to measure the MOSFET gate-to-source voltage and determine the proper time to switch instead of relying on a fixed time value. This feature allows the gate-driver dead time to adjust for variation in the system such a temperature drift and variation in the MOSFET parameters. An additional digital dead time (tDEAD) can be inserted and is adjustable through the registers on the SPI device.
The second component focuses on parasitic dV/dt gate turnon prevention. To implement this, the TDRIVE state machine enables a strong pulldown current (ISTRONG) on the opposite MOSFET gate whenever a MOSFET is switching. The strong pulldown happens for the tDRIVE duration. This feature helps remove parasitic charge that couples into the MOSFET gate when the half-bridge switch-node voltage slews rapidly.
The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a pair of VGS gate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a command to change the state of the half-bridge it begins to monitor the gate voltage of the external MOSFET. If, at the end of the tDRIVE period, the VGS voltage has not reached the proper threshold, the gate driver reports a fault. To ensure that a false fault is not detected, a tDRIVE time should be selected that is longer than the time required to charge or discharge the MOSFET gate. The tDRIVE time does not increase the PWM time and will terminate if another PWM command is received while active. Additional details on the TDRIVE settings are described in the Register Maps section for SPI device and in the Pin Diagrams section for hardware interface device.
NOTE
If the mode is set to independent PWM mode, then the IDRIVE current is automatically set for the IHOLD period.
Figure 21 shows an example of the TDRIVE state machine in operation.
Figure 21. TDRIVE State Machine