ZHCSI91B November 2017 – July 2018 DRV8304
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
請參考 PDF 數據表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SPI (nSCS, SCLK, SDI, SDO) | ||||||
| tREADY | SPI ready after after enable | VM > UVLO, ENABLE = 3.3 V | 1 | ms | ||
| tCLK | SCLK minimum period | 200 | ns | |||
| tCLKH | SCLK minimum high time | 100 | ns | |||
| tCLKL | SCLK minimum low time | 100 | ns | |||
| tSU_SDI | SDI input data setup time | 40 | ns | |||
| tHD_SDI | SDI input data hold time | 60 | ns | |||
| tDLY_SDO | SDO output data delay time | SCLK high to SDO valid | 60 | ns | ||
| tSU_nSCS | nSCS input setup time | 100 | ns | |||
| tHD_nSCS | nSCS input hold time | 100 | ns | |||
| tHI_nSCS | nSCS minimum high time before active low | 600 | ns | |||
| tEN_nSCS | nSCS enable time | nSCS low to SDO out of high impedance | 20 | ns | ||
| tDIS_nSCS | nSCS disable delay time | nSCS high to SDO high impedance | 20 | ns | ||
Figure 1. SPI Slave-Mode Timing Diagram