ZHCSI91B November 2017 – July 2018 DRV8304
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The DRV8304 device is an integrated 6-V to 38-V gate driver for 3-phase motor-drive applications. The device reduces system component count, cost, and complexity by integrating three independent half-bridge gate drivers, charge pump, and linear regulator for the high-side and low-side gate-driver supply voltages. A standard serial peripheral interface (SPI) provides a simple method for configuring the various device settings and reading fault diagnostic information through an external controller. Alternatively, a hardware interface (H/W) option allows for configuring the most commonly used settings through fixed external resistors.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 150-mA source, 300-mA sink peak currents with a 15-mA average output current. The high-side gate-drive supply voltage is generated using a doubler charge-pump architecture that regulates the VCP output to VVM + 10 V. The low-side gate-drive supply voltage is generated using a linear regulator from the VM power supply that regulates to 10 V. A smart gate-drive (SGD) architecture provides the ability to dynamically adjust the output gate-drive current strength allowing for the gate driver to control the power MOSFET VDS switching speed. This feature allows for the removal of external gate-drive resistors and diodes reducing bill of materials (BOM) component count, cost, and printed circuit board (PCB) area. The architecture also uses an internal state machine to protect against gate-drive short-circuit events, control the half-bridge dead time, and protect against dV/dt parasitic turnon of the external power MOSFET.
The DRV8304 device integrates three, bidirectional current-shunt amplifiers for monitoring the current level through each of the external half-bridges using a low-side shunt resistor. The gain setting of the shunt amplifier can be adjusted through the SPI (DRV8304S) or hardware (DRV8304H) interface with the SPI providing additional flexibility to adjust the output bias point.
In addition to the high level of device integration, the DRV8304 device provides a wide range of integrated protection features. These features include power-supply undervoltage lockout (UVLO), charge-pump undervoltage lockout (CPUV), VDS overcurrent monitoring (OCP), gate-driver short-circuit detection (GDF), and overtemperature shutdown (OTW and OTSD). Fault events are indicated by the nFAULT pin with detailed information available in the SPI registers on the SPI device version.
The DRV8304 device is available in 0.5-mm pin pitch, VQFN surface-mount packages. The VQFN package size is 6 mm × 6 mm.