ZHCSI91B November 2017 – July 2018 DRV8304
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 3-Phase Smart Gate Drivers
- 7.3.2 DVDD Linear Voltage Regulator
- 7.3.3 Pin Diagrams
- 7.3.4 Low-Side Current-Shunt Amplifiers
- 7.3.5 Gate-Driver Protection Circuits
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- Table 1. DRV8304S Register Map
- 7.6.1 Status Registers (DRV8304S Only)
- 7.6.2
Control Registers (DRV8304S Only)
- 7.6.2.1 Driver Control Register (Address = 0x02) [reset = 0x00]
- 7.6.2.2 Gate Drive HS Register (Address = 0x03) [reset = 0x377]
- 7.6.2.3 Gate Drive LS Register (Address = 0x04) [reset = 0x777]
- 7.6.2.4 OCP Control Register (Address = 0x05) [reset = 0x145]
- 7.6.2.5 CSA Control Register (Address = 0x06) [reset = 0x283]
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
請參考 PDF 數據表獲取器件具體的封裝圖。
機械數據 (封裝 | 引腳)
- RHA|40
散熱焊盤機械數據 (封裝 | 引腳)
- RHA|40
訂購信息
7.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
In this mode, the corresponding input pin independently controls each high-side and low-side gate driver. This control mode allows for the DRV8304 device to drive separate high-side and low-side loads with each half-bridge. These types of loads include unidirectional brushed DC motors, solenoids, and low-side and high-side switches. In this mode, if the system is configured in a half-bridge configuration, simultaneously turning on both the high-side and low-side MOSFETs causes shoot-through current in external MOSFETs and can cause them to damage.
Table 6. Independent PWM Mode Truth Table
| INLx | INHx | GLx | GHx |
|---|---|---|---|
| 0 | 0 | L | L |
| 0 | 1 | L | H |
| 1 | 0 | H | L |
| 1 | 1 | H | H |
Because the high-side and low-side VDS overcurrent monitors share the SHx sense line, using the monitors if both the high-side and low-side gate drivers of one half-bridge are split and being used is not possible. In this case, connect the SHx pin to the high-side driver and disable the VDS overcurrent monitors as shown in Figure 14.
Figure 14. Independent PWM High-Side and Low-Side Drivers If the half-bridge is used to implement only a high-side or low-side driver, using the VDS overcurrent monitors is still possible. Connect the SHx pin as shown in Figure 15 or Figure 16. The unused gate driver and the corresponding input can be left disconnected.
Figure 15. Single High-Side Driver 
Figure 16. Single Low-Side Driver