SLUSFH4A March 2025 – July 2025 BQ25858-Q1 , BQ25858B-Q1
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VAC / BAT POWER UP | |||||
| tACOV_DGL | Enter ACOV deglitch time, ACOV rising | 100 | μs | ||
| tACOVZ_DGL | Exit ACOV deglitch time, ACOV falling | 12 | ms | ||
| tACUV_DGL | Enter ACUV deglitch time, ACUV falling | 100 | μs | ||
| tACUVZ_DGL | Exit ACUV deglitch time, ACUV rising | 12 | ms | ||
| tTS_DGL | Deglitch time for TS threshold crossing | 25 | ms | ||
| tOVLD | Overload time during which ILIM2 is allowed, TOVLD_SET = 0 | 25 | ms | ||
| Overload time during which ILIM2 is allowed, TOVLD_SET = 1 | 50 | ms | |||
| tMAX | Time required before a new overload event is allowed after an original overload event. EN_OVLD_TMAX = 1 | 100 | ms | ||
| tOVLD_3L | Deglitch time before engaging ILIM2, allowing maximum current for this time. EN_OVLD_3L = 1 | 1 | ms | ||
| I2C INTERFACE | |||||
| fSCL | SCL clock frequency | 1000 | kHZ | ||
| DIGITAL CLOCK AND WATCHDOG | |||||
| tLP_WDT | I2C Watchdog reset time (EN_HIZ = 1, WATCHDOG[1:0] = 160s) | 100 | 160 | s | |
| tWDT | I2C Watchdog reset time (EN_HIZ = 0, WATCHDOG[1:0] = 160s) | 130 | 160 | s | |