SLUSFH4A March 2025 – July 2025 BQ25858-Q1 , BQ25858B-Q1
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
While operating the converter in reverse mode, the device monitors the reverse voltage, VVAC. When VVAC falls below the undervoltage threshold (programmable via SYSREV_UV register bit), the device stops switching, clears the EN_REV bit, and exits Reverse mode. During the over-voltage event duration, the REVERSE_STAT bit is cleared and the REVERSE_FLAG bit is set to indicate a fault in reverse mode. An INT pulse is also asserted to the host