SLUSFH4A March 2025 – July 2025 BQ25858-Q1 , BQ25858B-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Device Comparison
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Device Power-On-Reset
- 7.3.2 Device Power-Up From Battery Without Input Source
- 7.3.3 Device Power Up From Input Source
- 7.3.4 Power Management
- 7.3.5 Bidirectional Power Flow and Programmability
- 7.3.6 Switching Frequency Dithering Feature
- 7.3.7 Integrated 16-Bit ADC for Monitoring
- 7.3.8 Status Outputs (PG, STAT and INT)
- 7.3.9
Protections
- 7.3.9.1
Voltage and Current Monitoring
- 7.3.9.1.1 VAC Over-voltage Protection (VAC_OVP)
- 7.3.9.1.2 VAC Under-voltage Protection (VAC_UVP)
- 7.3.9.1.3 Reverse Mode Over-voltage Protection (REV_OVP)
- 7.3.9.1.4 Reverse Mode Under-voltage Protection (REV_UVP)
- 7.3.9.1.5 DRV_SUP Under-voltage and Over-voltage Protection (DRV_OKZ)
- 7.3.9.1.6 REGN Under-voltage Protection (REGN_OKZ)
- 7.3.9.2 Thermal Shutdown (TSHUT)
- 7.3.9.1
Voltage and Current Monitoring
- 7.3.10 Serial Interface
- 7.4 Device Functional Modes
- 7.5 BQ25858-Q1/858B-Q1 Registers
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
Typical Application (Buck-Boost configuration)
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 ACUV / ACOV Input Voltage Operating Window Programming
- 8.2.1.2.2 Switching Frequency Selection
- 8.2.1.2.3 Inductor Selection
- 8.2.1.2.4 Input (VAC) Capacitor
- 8.2.1.2.5 Output (VBAT) Capacitor
- 8.2.1.2.6 Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
- 8.2.1.2.7 Converter Fast Transient Response
- 8.2.1.3 Application Curves
- 8.2.2 Typical Application (Buck-only configuration)
- 8.2.1
Typical Application (Buck-Boost configuration)
- 8.3 Power Supply Recommendations
- 8.4 Layout
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數據表獲取器件具體的封裝圖。
機械數據 (封裝 | 引腳)
- RRV|36
散熱焊盤機械數據 (封裝 | 引腳)
- RRV|36
訂購信息
7.3.8.3 Interrupt to Host (INT)
In some applications, the host does not always monitor the power converter operation. The INT pin notifies the system host on the device operation. By default, the following events will generate an active-low, 256μs INT pulse.
- Valid input source conditions detected (see conditions for PG pin)
- Valid input source conditions removed (see conditions for PG pin)
- Entering IAC_DPM regulation through register or IIN pin
- Entering VAC_DPM regulation through register or ACUV pin
- I2C Watchdog timer expired
- Converter status changes state (CHARGE_STAT value change)
- TS_STAT changes state (TS_STAT value change)
- Junction temperature shutdown (TSHUT)
- A rising edge on any of the *_STAT bits
Each one of these INT sources can be masked off to prevent INT pulses from being sent out when they occur. Three bits exist for each one of these events:
- The STAT bit holds the current status of each INT source
- The FLAG bit holds information on which source produced an INT, regardless of the current status
- The MASK bit is used to prevent the device from sending out INT for each particular event
When one of the above conditions occurs (a rising edge on any of the *_STAT bits), the device sends out an INT pulse and keeps track of which source generated the INT via the FLAG registers. The FLAG register bits are automatically reset to zero after the host reads them, and a new edge on STAT bit is required to re-assert the FLAG.
Figure 7-6 INT Generation Behavior
Example