SLUSFH4A March 2025 – July 2025 BQ25858-Q1 , BQ25858B-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Device Comparison
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Device Power-On-Reset
- 7.3.2 Device Power-Up From Battery Without Input Source
- 7.3.3 Device Power Up From Input Source
- 7.3.4 Power Management
- 7.3.5 Bidirectional Power Flow and Programmability
- 7.3.6 Switching Frequency Dithering Feature
- 7.3.7 Integrated 16-Bit ADC for Monitoring
- 7.3.8 Status Outputs (PG, STAT and INT)
- 7.3.9
Protections
- 7.3.9.1
Voltage and Current Monitoring
- 7.3.9.1.1 VAC Over-voltage Protection (VAC_OVP)
- 7.3.9.1.2 VAC Under-voltage Protection (VAC_UVP)
- 7.3.9.1.3 Reverse Mode Over-voltage Protection (REV_OVP)
- 7.3.9.1.4 Reverse Mode Under-voltage Protection (REV_UVP)
- 7.3.9.1.5 DRV_SUP Under-voltage and Over-voltage Protection (DRV_OKZ)
- 7.3.9.1.6 REGN Under-voltage Protection (REGN_OKZ)
- 7.3.9.2 Thermal Shutdown (TSHUT)
- 7.3.9.1
Voltage and Current Monitoring
- 7.3.10 Serial Interface
- 7.4 Device Functional Modes
- 7.5 BQ25858-Q1/858B-Q1 Registers
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
Typical Application (Buck-Boost configuration)
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 ACUV / ACOV Input Voltage Operating Window Programming
- 8.2.1.2.2 Switching Frequency Selection
- 8.2.1.2.3 Inductor Selection
- 8.2.1.2.4 Input (VAC) Capacitor
- 8.2.1.2.5 Output (VBAT) Capacitor
- 8.2.1.2.6 Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
- 8.2.1.2.7 Converter Fast Transient Response
- 8.2.1.3 Application Curves
- 8.2.2 Typical Application (Buck-only configuration)
- 8.2.1
Typical Application (Buck-Boost configuration)
- 8.3 Power Supply Recommendations
- 8.4 Layout
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RRV|36
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RRV|36
訂購(gòu)信息
5 Pin Configuration and Functions
Figure 5-1 BQ25858-Q1/858B-Q1, RRV
Package36-Pin VQFNTop ViewTable 5-1 Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| SCL | 1 | DI | I2C Interface Clock – Connect SCL to the logic rail through a 10kΩ resistor. |
| SDA | 2 | DIO | I2C Interface Data – Connect SDA to the logic rail through a 10kΩ resistor. |
| INT | 3 | DO | Open Drain Interrupt Output – Connect the INT pin to a logic rail via 10kΩ resistor. The INT pin sends an active low, 256μs pulse to host to report the converter device status and faults. |
| STAT | 4 | DO | Open Drain Status Output – Connect to the pull up rail via 10kΩ resistor. The STAT pin function can be disabled when DIS_STAT_PIN bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT_ON bit. |
| NC | 5 | - | No Connect - Leave this pin floating, do not tie to PGND |
| PG | 6 | DO | Open Drain Active Low Power Good Indicator – Connect to the pull up rail via 10kΩ resistor. LOW indicates a good input source if VAC is within the programmed ACUV / ACOV operating window. The PG pin function can be disabled when DIS_PG_PIN bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT3_ON bit. |
| CE | 7 | DIO | Active Low Enable Pin – Power conversion is enabled when EN_CHG bit is 1 and CE pin is LOW. CE pin must be pulled HIGH or LOW, do not leave floating. The CE pin function can be disabled when DIS_CE_PIN bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT4_ON bit. |
| TS / NC | 8 | AI | Temperature Qualification
Voltage Input – This pin's function is normally disabled. If not needed, leave
this pin floating. To enable pin functionality, set EN_TS register bit to 1. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to PGND. Power conversion suspends when TS pin voltage is out of range. Recommend 103AT-2 10kΩ thermistor. |
| IOUT | 9 | AI | Output Current Limit Setting – IOUT pin sets the maximum output current, and can be used to monitor the output current. A programming resistor to PGND is used to set the output current limit as IIOUT = KIOUT / RIOUT. When the device is under output current regulation, the voltage at IOUT pin is VREF_IOUT. When IOUT pin voltage is less than VREF_IOUT, the actual output current can be calculated as: IOUT = KIOUT x VIOUT / ( RIOUT x VREF_IOUT). The actual output current limit is the lower of the limits set by IOUT pin or the IOUT_REG register bits. This pin function can be disabled when EN_IOUT_PIN bit is 0. If IOUT pin is not used, this pin should be pulled to PGND, do not leave floating. |
| IIN | 10 | AI | Input Current Limit Setting – IIN pin sets the maximum input current, and can be used to monitor the input current. A programming resistor to PGND is used to set the input current limit as ILIM = KILIM / RIIN. When the device is under input current regulation, the voltage at IIN pin is VREF_IILIM. When IIN pin voltage is less than VREF_ILIM, the actual input current can be calculated as: IAC = KILIM x VIIN / ( RIIN x VREF_ILIM). The actual input current limit is the lower of the limits set by IIN pin or the IAC_DPM register bits. This pin function can be disabled when EN_IIN_PIN bit is 0. If IIN pin is not used, this pin should be pulled to PGND, do not leave floating. |
| NC | 11 | - | No Connect - Leave this pin floating , do not tie to PGND |
| VO_SNS | 12 | AI | Output Voltage Sensing – Kelvin connect directly to the output voltage regulation point. |
| SRN | 13 | AI | Current-Sense Resistor, Negative Input – A 0.47-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the SRN pin to PGND for common-mode filtering. |
| SRP | 14 | AI | Current-Sense Resistor, Positive Input – A 0.47-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the SRP pin to PGND for common-mode filtering. |
| NC | 15 | - | No Connect - Leave this pin floating, do not tie to PGND |
| NC | 16 | - | No Connect - Leave this pin floating, do not tie to PGND |
| MODE | 17 | AI | Mode Programming resistor –Connect a resistor from this pin to PGND to select between buck-boost or buck-only operation. Refer to MODE Pin Configuration section for more details. |
| SW2 | 18 | AI | Boost Side Half Bridge Switching Node – Boost side half-bridge switching node |
| HIDRV2 | 19 | AO | Boost Side High-Side Gate Driver – Connect to the boost high-side N-channel MOSFET gate. |
| BTST2 | 20 | P | Boost Side High-Side Power MOSFET Gate Driver Power Supply – Connect a capacitor between BTST2 and SW2 to provide bias to the high-side MOSFET gate driver. |
| LODRV2 | 21 | AO | Boost Side Low-Side Gate Driver – Connect to the boost low-side N-channel MOSFET gate. |
| PGND | 22 | - | Power Ground Return – The high current ground connection for the low-side gate drivers. |
| DRV_SUP | 23 | P | Converter Gate Drive Supply Input – Voltage on this pin is used to drive the gates of buck-boost converter switching FET. Connect a 4.7-μF ceramic capacitor from DRV_SUP to power ground. REGN LDO voltage can be used as the gate driver supply for all switching FETs by connecting REGN to DRV_SUP pin. In high-voltage applications, it is possible to directly provide the DRV_SUP voltage with an external supply up to 12 V to achieve higher switching efficiency. See Section 7.3.3.3 for more details. |
| REGN | 24 | P | Converter Internal Linear Regulator Output – Connect a 4.7-μF ceramic capacitor from REGN to power ground. REGN LDO voltage can be used as the gate driver supply for all switching FETs by connecting REGN to DRV_SUP pin. In high-voltage applications, it is possible to directly provide the DRV_SUP voltage with an external supply up to 12 V to achieve higher switching efficiency. See Section 7.3.3.3 for more details. |
| LODRV1 | 25 | AO | Buck Side Low-Side Gate Driver – Connect to the buck low-side N-channel MOSFET gate. |
| BTST1 | 26 | P | Buck Side High-Side Power MOSFET Gate Driver Power Supply – Connect a capacitor between BTST1 and SW1 to provide bias to the high-side MOSFET gate driver. |
| HIDRV1 | 27 | AO | Buck Side High-Side Gate Driver – Connect to the buck high-side N-channel MOSFET gate. |
| SW1 | 28 | AI | Buck Side Half Bridge Switching Node – Buck side half-bridge switching node |
| ACN | 29 | AI | Adapter Current-Sense Resistor, Negative Input A 0.47-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the ACN pin to PGND for common-mode filtering. |
| ACP | 30 | AI | Adapter Current-Sense Resistor, Positive Input A 0.47-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the ACP pin to PGND for common-mode filtering |
| NC | 31 | - | No Connect - Leave this pin floating, do not tie to PGND |
| VAC | 32 | P | Input Voltage Detection and Power VAC is the input bias to power the IC. Connect a 1μF capacitor from pin to PGND. When Reverse Mode is enabled, pin 32 is regulated to VAC_REV. |
| 33 | |||
| ACUV | 34 | AI | VAC Undervoltage Comparator Input – Connect a resistor divider from VAC to PGND to program the undervoltage protection. When this pin falls below VREF_ACUV, the device stops power conversion. The hardware limit for input voltage regulation reference is VACUV_DPM. The actual input voltage regulation setting is the higher of the pin-programmed value and the VAC_DPM register value. If ACUV programming is not used, pull this pin to VAC, do not leave floating. |
| ACOV | 35 | AI | VAC Overvoltage Comparator Input – Connect a resistor divider from VAC to PGND to program the overvoltage protection. When this pin rises above VREF_ACOV, the device stops power conversion. If ACOV programming is not used, pull this pin to PGND, do not leave floating. |
| FSW_SYNC | 36 | DAI | Switching Frequency and Synchronization Input – An external resistor is connected to the FSW_SYNC pin and PGND to set the nominal switching frequency. This pin can also be used to synchronize the PWM controller to an external clock. |
| Thermal Pad | 37 | - | Exposed pad beneath the IC – Always solder the thermal pad to the board, and have vias on the thermal pad plane star-connecting to PGND and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat. |