SPRAC21A June 2016 – June 2019 OMAP-L132 , OMAP-L138 , TDA2E , TDA2EG-17 , TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2P-ABZ , TDA2P-ACD , TDA2SA , TDA2SG , TDA2SX , TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV
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TDA2xx and TDA2ex Performance
- Trademarks
- 1 SoC Overview
- 2 Cortex-A15
- 3 System Enhanced Direct Memory Access (System EDMA)
- 4 DSP Subsystem EDMA
- 5 Embedded Vision Engine (EVE) Subsystem EDMA
- 6 DSP CPU
- 7 Cortex-M4 (IPU)
- 8 USB IP
- 9 PCIe IP
- 10 IVA-HD IP
- 11 MMC IP
- 12 SATA IP
- 13 GMAC IP
- 14 GPMC IP
- 15 QSPI IP
- 16 Standard Benchmarks
- 17
Error Checking and Correction (ECC)
- 17.1 OCMC ECC Programming
- 17.2 EMIF ECC Programming
- 17.3 EMIF ECC Programming to Starterware Code Mapping
- 17.4 Careabouts of Using EMIF ECC
- 17.5 Impact of ECC on Performance
- 18 DDR3 Interleaved vs Non-Interleaved
- 19 DDR3 vs DDR2 Performance
- 20 Boot Time Profile
- 21 L3 Statistics Collector Programming Model
- 22 Reference
- Revision History
15 QSPI IP
The QSPI is a Serial Peripheral Interface module that allows for single, dual, or quad read access to external memory devices. The Quad SPI protocol is a 6-pin interface that supports master mode only in 3-pin, 4-pin, or 6-pin configurations. Up to 4 chip selects are supported. This Serial Flash Interface does not directly support all details of writing to serial Flash devices and also does not support dual/quad write.
This device supports a normal configuration port mode as well as a memory-mapped interface, which provides a direct memory interface for accessing data from the external SPI device, simplifying software requirements.
- Configuration Port Mode: In this mode, commands can be sent through the core SPI to communicate with a serial Flash device, but software must load the command into the SPI data transfer register along with additional configuration fields, perform the byte transfer, then place the data to be sent (or configure for receive) along with additional configuration fields, and perform that transfer. Reads and writes to serial Flash devices are more specific. First, the read or write command byte is sent, followed by 1 to 4 bytes of address (corresponding to the address to read/write), then followed by the data write/receive phase. Data is always sent in 8-bit chunks (byte oriented). Once the address has been loaded, data can be continuously read or written and internally to the serial Flash device, the address will automatically increment to each byte address.
- Memory-Mapped Mode: This mode supports long transfers through a frame style sequence. In its generic SPI use mode (referred to as core SPI), a word can be defined up to 32 bits and multiple words can be transferred during a single access. For each word, the processor will need to read or write the new data and then tell the SPI module to continue the current operation. Using this sequence, up to 4096 words (32-bit max) can be transferred in a single SPI read or write operation. While this allows for the greatest flexibility in terms of connecting to various types of devices, it does not lend itself to a memory-mapped type device such as a serial Flash device.
A block diagram representation of QSPI controller is shown in Figure 40.
Figure 40. QSPI Block Diagram