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7.2.2 Cache Enable

Table 33. IPU RD, WR, COPY Performance With Cache Enabled
(Policy: Write-Back, No Write-Allocate), 32-Bit Word Size

Initiator/Operation	Source	Destination	Size (KB)	Bandwidth (MB/s)
M4 WR	CPU Register	DDR	4096	268.03
M4 RD	DDR	CPU Register	4096	93.59
M4 COPY	DDR	DDR	4096	111.39
M4 WR	CPU Register	OCMC	128	276.12
M4 RD	OCMC	CPU Register	128	158.76
M4 COPY	OCMC	OCMC	128	177.34

Table 34. Impact of Different Cache Policies on IPU CPU Performance, 32-Bit Word Size

Initiator/ Operation	Source	Destination	Size (KB)	Write-Back, Write Allocate	Write-Back, No-Write Allocate	Write-Through, Write Allocate	Write-Through, No-Write Allocate
M4 WR	CPU Register	DDR	4096	75.2	268.03	267.98	267.03
M4 RD	DDR	CPU Register	4096	93.48	93.59	93.15	93.61
M4 COPY	DDR	DDR	4096	80.56	111.39	110.44	111.42
M4 WR	CPU Register	OCMC	128	148.78	276.12	269.51	269.6
M4 RD	OCMC	CPU Register	128	158.73	158.76	155.07	158.73
M4 COPY	OCMC	OCMC	128	141.7	177.34	174.21	177.78

Transfer speed depends on Cache allocation policy.
No-Write allocate policy gives better transfer performance for write operation than Write allocate policy. In case of write allocate policy, write miss causes cache line size written back to next level memory and new line read into the cache. For larger data transfer, due to frequent misses it will add extra latency and reduces transfer speed.
Both Write-back and Write-through policies can use either of Write allocate or No-write allocate policy. But generally paired in this way: a Write-back policy uses Write allocate, hoping for subsequent writes to the same location, which is now cached; a Write-through policy uses No-write allocate policy, here subsequent writes have no advantage as they still need to be written to backing store.

Table 35. Impact of Word Size Used on IPU CPU Performance
(Cache Policy: Write-Back, No-Write Allocate)

Initiator/Operation	Word Size	Source	Destination	Size (KB)	Bandwidth (MB/s)
M4 WR	32 bit	CPU Register	DDR	4096	267.95
M4 RD	32 bit	DDR	CPU Register	4096	93.17
M4 COPY	32 bit	DDR	DDR	4096	110.42
M4 WR	64 bit	CPU Register	DDR	8192	179.88
M4 RD	64 bit	DDR	CPU Register	8192	78.09
M4 COPY	64 bit	DDR	DDR	8192	100.2

Table 36 shows the performance difference between with and without loop unroll. In case of without loop unroll (when there is only one read, write, and copy operation in the loop) gives inferior performance compared to with loop unroll as it checks for loop condition after every word transfer in case of without loop unroll. In case of with loop unroll, it checks for loop condition only after a 128 words (write or read) or a 32 words (copy) transfer.

Table 36. IPU RD, WR, COPY Performance With Cache Enabled
(Policy: Write-Back, No-Write Allocate), 32-Bit Word Size

Initiator/Operation	Source	Destination	Size (KB)	Bandwidth (MB/s) (with loop unroll)	Bandwidth (MB/s) (without loop unroll)
M4 WR	CPU Register	DDR	4096	267.76	203.08
M4 RD	DDR	CPU Register	4096	93.19	69.2
M4 COPY	DDR	DDR	4096	110.6	104.24

7.2.2 Cache Enable

Table 33. IPU RD, WR, COPY Performance With Cache Enabled (Policy: Write-Back, No Write-Allocate), 32-Bit Word Size

Table 34. Impact of Different Cache Policies on IPU CPU Performance, 32-Bit Word Size

Table 35. Impact of Word Size Used on IPU CPU Performance (Cache Policy: Write-Back, No-Write Allocate)

Table 36. IPU RD, WR, COPY Performance With Cache Enabled (Policy: Write-Back, No-Write Allocate), 32-Bit Word Size

Table 33. IPU RD, WR, COPY Performance With Cache Enabled
(Policy: Write-Back, No Write-Allocate), 32-Bit Word Size

Table 35. Impact of Word Size Used on IPU CPU Performance
(Cache Policy: Write-Back, No-Write Allocate)

Table 36. IPU RD, WR, COPY Performance With Cache Enabled
(Policy: Write-Back, No-Write Allocate), 32-Bit Word Size