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SPRAC21A June 2016 – June 2019 OMAP-L132 , OMAP-L138 , TDA2E , TDA2EG-17 , TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2P-ABZ , TDA2P-ACD , TDA2SA , TDA2SG , TDA2SX , TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV

18.1 Interleaved versus Non-Interleaved Setup

TDA2xx supports two external memory controllers (EMIF). These EMIFs can be configured in interleaved and non-interleaved modes. In the non-interleaved mode of EMIF operation, the internal banks of 32-bit SDRAM can be accessed. In interleaved mode, the internal banks of two 32-bit SDRAMs can be accessed. Interleaving is configured to occur at 128-byte, 256-byte, or 512-byte granularity. For example, if 128-byte granularity interleaving is set it means the first 128-bytes are from EMIF1, the second 128-bytes are from EMIF2, the third 128-bytes are from EMIF1, and so on. Interleaving is controlled by the DMM_LISA_MAP registers, shown in Table 90.

Table 90. DMM_LISA_MAP_x

Bits	Field Name	Description	Type	Reset
31:24	SYS_ADDR	DMM system section address MSB.	R/W	0x0
23	RESERVED	Reserved	R	0x0
22:20	SYS_SIZE	DMM system section size.	R/W	0x0
		0: 16-MiB section
		1: 32-MiB section
		2: 64-MiB section
		3: 128-MiB section
		4: 256-MiB section
		5: 512-MiB section
		6: 1-GiB section
		7: 2-GiB section
19:18	SDRC_INTL	SDRAM controller interleaving mode.	R/W	0x0
		0: No interleaving
		1: 128-byte interleaving
		2: 256-byte interleaving
		3: 512-byte interleaving
17:16	SDRC_ADDRSPC	SDRAM controller address space	R/W	0x0
15:10	RESERVED	Reserved	R	0x0
9:8	SDRC_MAP	SDRAM controller mapping.	R/W	0x0
		0: Unmapped
		1: Mapped on SDRC 0 only (not interleaved).
		2: Mapped on SDRC 1 only (not interleaved).
		3: Mapped on SDRC 0 and SDRC 1 (interleaved). If this setting is used, SYS_SIZE must at least be equal to 32-MiB.
7:0	SDRC_ADDR	SDRAM controller address MSB.	R/W	0x0

The configuration used for non-interleaved DDR3 is as follows: (512-MB, Non-Interleaved) DDR3 running at 532 MHz.

Note that the value of the LISA map should be the same between the MA LISA map and the DMM Lisa Map.

//MA_LISA_MAP_i
WR_MEM_32(0x482AF040, 0x80500100);
WR_MEM_32(0x482AF044, 0xA0500200);
//DMM_LISA_MAP_i
WR_MEM_32(0x4E000040, 0x80500100);
WR_MEM_32(0x4E000044, 0xA0500200);

The configuration used for interleaved DDR3 is as follows: (1-GB, 128-Byte Interleaved) DDR3 running at 532 MHz.

Note that the value of the LISA map should be the same between the MA LISA map and the DMM Lisa Map.

//MA_LISA_MAP_i
WR_MEM_32(0x482AF040, 0x80640300);
WR_MEM_32(0x482AF044, 0x00000000);
//DMM_LISA_MAP_i
WR_MEM_32(0x4E000040, 0x80640300);
WR_MEM_32(0x4E000044, 0x00000000);