SPRAC21A June 2016 – June 2019 OMAP-L132 , OMAP-L138 , TDA2E , TDA2EG-17 , TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2P-ABZ , TDA2P-ACD , TDA2SA , TDA2SG , TDA2SX , TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV
Following is the C code for the L2 Stride-Jmp Write function. The difference from the earlier pipeline read is as highlighted.
void l2_stride_jmp_write(unsigned byte_cnt)
{
long long *restrict dst = (long long *)ext_buf[1];
unsigned int wrStartTime, wrStopTime;
int i;
_nassert((int)dst == 0);
wrStartTime = CSL_tscRead();
#pragma UNROLL(2)
for (i=0; i<byte_cnt/8; i+=16 )
{
dst[i] = 0xDEADDEAD;
}
wrStopTime = CSL_tscRead();
WBINVALIDATE
wrDuration = (float)(wrStopTime-wrStartTime)/(DSP_FREQ/1000);
}
Following is the analysis of the scheduled iteration is given out by the compiler. The pipeline is the same as the pipeline write function with the difference of additional ADD operations happening in parallel with the two store operations.
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop found in file : ../pipeline_loop.c
;* Loop source line : 88
;* Loop opening brace source line : 95
;* Loop closing brace source line : 97
;* Loop Unroll Multiple : 2x
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 1
;* Unpartitioned Resource Bound : 1
;* Partitioned Resource Bound(*) : 1
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 1* 1*
;* .D units 1* 1*
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 1* 1*
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 0 0 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1* 1*
;* Bound(.L .S .D .LS .LSD) 1* 1*
;*
;* Searching for software pipeline schedule at ...
;* ii = 1 Schedule found with 2 iterations in parallel
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MV A4,B4
;* MV A5,B5
;*
;* SINGLE SCHEDULED ITERATION
;*
;* $C$C94:
;* 0 STDW .D2T2 B5:B4,*B6 ; |96| ^
;* || ADDK .S2 256,B6 ; |96| ^
;* || STDW .D1T1 A5:A4,*A3 ; |96| ^
;* || ADDK .S1 256,A3 ; |96| ^
;* || SPBR $C$C94
;* 1 NOP 1
;* 2 ; BRANCHCC OCCURS {$C$C94} ; |88|
;*----------------------------------------------------------------------------*