17 Error Checking and Correction (ECC)
TDA2xx and TDA2ex Error Checking and Correction (ECC) implemented on the OCMC RAM 1, 2, and 3, and EMIF. The ECC memory wrappers can perform single error correction and double error detection.
Overview of the OCMC ECC features are:
- Error correction and detection: Single Error Correction and Dual Error Detection (SECDED)
- 9-bit Hamming Error Correction Code (ECC) calculated on 128 data word concatenated with memory address bits
- Hamming distance of 4 (single error detection/correction and double error detection; triple error detection (TED) is NOT supported).
- Enable/Disable/Test-Suspend Mode Control through control register
- Read transaction single bit error correction
- Hardware Automated write back of correctable detected error
- Exclude repeated addresses from correctable error address trace history
- ECC valid for all write transactions to enabled region
- 128-bit aligned/128-bit length writes have no additional overhead
- Sub 128-bit writes supported by way of read-modify-write
- ECC Error Status Reporting features:
- Corrected Error Address Trace History Buffer (FIFO): Depth of 4
- Non-correctable error address trace history buffer (including DED): Depth of 4
- Interrupt Generation for correctable/uncorrectable detected errors
- ECC Diagnostics Configuration:
- SEC/DED/Addr Error Event Counters
- Programmable SEC/DED/Addr Error Event Counter Exception Threshold registers
- Corrected Single Error bit distribution history
- Register control for enable and disabling of diagnostics
- Configuration registers and ECC status accessible through OCP MMR interface (L4)
The EMIF ECC features are:
- ECC on SDRAM data bus.
- 7-bit ECC over 32-bit quanta or 6-bit ECC over 16-bit quanta in Narrow mode.
- 1-bit correction and 2-bit detection.
- Programmable address ranges to define ECC protected region.
- ECC calculated and stored on all writes to ECC protected address region.
- ECC verified on all reads from ECC protected address region.
- Statistics for 1-bit ECC and 2-bit ECC errors.
- All DDRs must have the same data bus width. The ECC DDR must support the same data bus width as the normal DDR ICs for data. The total width of the ECC DDR data bus is 8 bits.