SPRAC21A June 2016 – June 2019 OMAP-L132 , OMAP-L138 , TDA2E , TDA2EG-17 , TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2P-ABZ , TDA2P-ACD , TDA2SA , TDA2SG , TDA2SX , TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV
-
TDA2xx and TDA2ex Performance
- Trademarks
- 1 SoC Overview
- 2 Cortex-A15
- 3 System Enhanced Direct Memory Access (System EDMA)
- 4 DSP Subsystem EDMA
- 5 Embedded Vision Engine (EVE) Subsystem EDMA
- 6 DSP CPU
- 7 Cortex-M4 (IPU)
- 8 USB IP
- 9 PCIe IP
- 10 IVA-HD IP
- 11 MMC IP
- 12 SATA IP
- 13 GMAC IP
- 14 GPMC IP
- 15 QSPI IP
- 16 Standard Benchmarks
- 17
Error Checking and Correction (ECC)
- 17.1 OCMC ECC Programming
- 17.2 EMIF ECC Programming
- 17.3 EMIF ECC Programming to Starterware Code Mapping
- 17.4 Careabouts of Using EMIF ECC
- 17.5 Impact of ECC on Performance
- 18 DDR3 Interleaved vs Non-Interleaved
- 19 DDR3 vs DDR2 Performance
- 20 Boot Time Profile
- 21 L3 Statistics Collector Programming Model
- 22 Reference
- Revision History
1.4.1 Bandwidth Regulators
The bandwidth regulators prevent master NIUs from consuming too much bandwidth of a link or a slave NIU that is shared between several data flows: packets are then transported at a slower rate. The value of a bandwidth can be programmed in the bandwidth regulator. When the bandwidth is below the programmed value, the pressure bit is set to 1, giving priority to this master. When the bandwidth is above the programmed value, the pressure bit is set to 0 and the concerned master has the same weight as others.
Bandwidth regulators are by default enabled in interconnect with the default configuration such that the expected average bandwidth is set to zero. With any amount of traffic, the actual average bandwidth seen will be greater than zero and, hence, lower pressure bits (00b) will be enabled by default. You need to program the regulators to achieve the desired regulation in case of concurrences. If set, the bandwidth regulator discards the L3 initiator priority using the device control module.
Bandwidth regulators:
- Regulates the traffic through priority; does not really stop traffic.
- Sets low-priority, by default. On setting a valid bandwidth other than 0, the initiator is given higher priority when the bandwidth is lower than the threshold.
- Does not set an upper limit, If there is no contention, the initiator can claim full share as well.
Bandwidth regulator available for the following IPs:
- MMU2
- EVE1, EVE2, EVE3, EVE4 – both TC0 and TC1
- DSP1, DSP2 MDMA (CPU access port)
- DSP1, DSP2 EDMA
- IVA
- GPU
- GMAC
- PCIe
Figure 3. TDA2xx and TDA2ex Bandwidth Regulator Mechanism Illustration Programming API for the bandwidth regulator is:
set_bw_regulator(int port, unsigned int average_bw, unsigned int time_in_us
{
unsigned int base_address = get_bw_reg_base_address(port);
WR_REG32(base_address+0x8,(int)(ceil(average_bw/8.3125));
WR_REG32(base_address+0xC,(time_in_us*average_bw));
WR(REG32(base_address+0x14,0x1);
}
get_bw_reg_base_address(port) {
if ( port == "EVE1_TC0" ) { return
L3_NOC_AVATAR__DEBUGSS_CS_DAP_INIT_OCP_L3_NOC_AVATAR_CLK1_EVE1_TC0_BW_REGULATOR;
}
...
}