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ZHCSP86E May 2020 – February 2024 UCC5350-Q1

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

D|8
- MSOI002K
DWV|8
- MPDS382B

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

9.2.2.2 Gate-Driver Output Resistor

The external gate-driver resistors, R_G(ON) and R_G(OFF) are used to:

Limit ringing caused by parasitic inductances and capacitances
Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery
Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss
Reduce electromagnetic interference (EMI)

The output stage has a pull-up structure consisting of a P-channel MOSFET and an N-channel MOSFET in parallel. The combined typical peak source current is 10 A for UCC5350-Q1. Use Equation 1 to estimate the peak source current.

Equation 1.

I_{O H} = \frac{V_{C C 2} - V_{E E 2}}{R_{N M O S} | | R_{O H} + R_{G O N} + R_{G F E T_I n t}}

where

R_ON is the external turn-on resistance, which is 2.2 Ω in this example.
R_{GFET_Int} is the power transistor internal gate resistance, found in the power transistor data sheet. We will assume 1.8Ω for our example.
I_OH is the typical peak source current which is the minimum value between 10 A, the gate-driver peak source current, and the calculated value based on the gate-drive loop resistance.

In this example, the peak source current is approximately 3.36 A as calculated in Equation 2.

Equation 2.

I_{O H} = \frac{V_{C C 2} - V_{E E 2}}{R_{N M O S} | | R_{O H} + R_{G O N} + R_{G F E T_I n t}} = \frac{18 V}{1.54 Ω | | 12 Ω + 2.2 Ω + 1.8 Ω} \approx 3.36 A

Similarly, use Equation 3 to calculate the peak sink current.

Equation 3.

I_{O L} = \frac{V_{C C 2} - V_{E E 2}}{R_{O L} + R_{G O F F} + R_{G F E T_I n t}}

where

R_OFF is the external turn-off resistance, which is 2.2 Ω in this example.
I_OL is the typical peak sink current which is the minimum value between 10 A, the gate-driver peak sink current, and the calculated value based on the gate-drive loop resistance.

In this example, the peak sink current is the minimum value between Equation 4 and 10 A.

Equation 4.

I_{O L} = \frac{V_{C C 2} - V_{E E 2}}{R_{O L} + R_{G O F F} + R_{G F E T_I n t}} = \frac{18 V}{0.26 Ω + 2.2 Ω + 1.8 Ω} \approx 4.23 A

Note:

The estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot and undershoot. Therefore, TI strongly recommends that the gate-driver loop should be minimized. Conversely, the peak source and sink current is dominated by loop parasitics when the load capacitance (C_ISS) of the power transistor is very small (typically less than 1 nF) because the rising and falling time is too small and close to the parasitic ringing period.