ZHCSP86E May 2020 – February 2024 UCC5350-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 說明（續）
- 5 Pin Configuration and Function
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Ratings
- 6.6 Insulation Specifications for D Package
- 6.7 Insulation Specifications for DWV Package
- 6.8 Safety-Related Certifications For D Package
- 6.9 Safety-Related Certifications For DWV Package
- 6.10 Safety Limiting Values
- 6.11 Electrical Characteristics
- 6.12 Switching Characteristics
- 6.13 Insulation Characteristics Curves
- 6.14 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Revision History
- 14Mechanical, Packaging, and Orderable Information
5 Pin Configuration and Function
Figure 5-1 UCC5350MC-Q18-Pin SOICTop View
Figure 5-2 UCC5350SB-Q1
8-Pin SOICTop
ViewTable 5-1 Pin Functions
| PIN | TYPE(1) | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | NO. | ||
| UCC5350MC-Q1 | UCC5350SB-Q1 | |||
| CLAMP | 7 | — | I | Active Miller-clamp input used to prevent false turn-on of the power switches found on the 'M' version. |
| GND1 | 4 | 4 | G | Input ground. All signals on the input side are referenced to this ground. |
| IN+ | 2 | 2 | I | Noninverting gate-drive voltage-control input. The IN+ pin has a CMOS input threshold. This pin is pulled low internally if left open. Use Table 8-4 to understand the input and output logic of these devices. |
| IN– | 3 | 3 | I | Inverting gate-drive voltage control input. The IN– pin has a CMOS input threshold. This pin is pulled high internally if left open. Use Table 8-4 to understand the input and output logic of these devices. |
| OUT | 6 | — | O | Gate-drive output found on the 'M' version |
| OUTH | — | 6 | O | Gate-drive pullup output found on the 'S' version |
| OUTL | — | 7 | O | Gate-drive pulldown output found on the 'S' version |
| VCC1 | 1 | 1 | P | Input supply voltage. Connect a locally decoupled capacitor to GND1. Use a low-ESR or ESL capacitor located as close to the device as possible. |
| VCC2 | 5 | 5 | P | Positive output supply rail. Connect a locally decoupled capacitor to VEE2. Use a low-ESR or ESL capacitor located as close to the device as possible. |
| VEE2 | 8 | 8 | G | Ground pin. Connect to MOSFET source or IGBT emitter. Connect a locally decoupled capacitor from VCC2 to VEE2. Use a low-ESR or ESL capacitor located as close to the device as possible. |
(1) P = Power, G = Ground, I = Input,
O = Output