As shown in Figure 7-7, the S13 pin (switched 13-V rail) is used to perform bias-power management for a primary-side GaN power IC, along with an example application where it also powers a PFC controller. This configuration enables to minimize the power-loss contribution to so-called tiny-load input power and stand-by power.

S13 is sourced by P13 through an internal 2.8-? switch controlled by the RUN pin. Figure 7-8 illustrates the power-up sequence of the S13 pin. When RUN is high, the S13 decoupling capacitor is charged up to 13 V and the charge current is controlled by an internal soft-start current limiter. The S13-pin voltage must increase above the 10-V power-good threshold (V_S13(OK)) in order to initiate PWML switching of each burst cycle. When RUN is low, V_S13 is discharged by the loading on S13. The power-on delay of the GaN power IC on the S13 pin must be less than 2 μs to be responsive to PWML. If not, the VDD or P13 pin may be a more suitable bias supply for a GaN power IC with long power-on delay, but the wait-state power consumption is compromised. A 22-nF ceramic capacitor as C_S13(ZVSF) is recommended. If the S13 pin is not used, it can be connected to the P13 pin in order to eliminate the delay effect on PWML switching in every low-frequency burst cycle.

Figure 7-7 Power Management Function for a GaN Power IC and PFC Controller

Figure 7-8 Power-up Sequence of the S13 Pin

When the S13 pin supplies both the GaN power IC and a PFC controller at the same time, a low-voltage rectifier diode (D_S13) between the S13 pin and the PFC controller bias VCC pin is needed, so the local decoupling capacitor for each powered controller can be separated. The decoupling capacitor of the PFC controller (C_S13(PFC)) is usually larger than the one for a GaN power IC, such that the bias voltage of the GaN power IC discharges more quickly without affecting the PFC bias voltage and PFC output voltage regulation. If the S13 pin supplies a PFC controller only, the rectifier diode is not needed.

During start-up before VDD reaches the V_VDD(ON) threshold, the S13 switch stays off, so the S13-pin loading does not consume any of the charging current of VDD capacitor flowing from SWS pin to VDD pin, thereby enabling a fast start-up sequence. Under this condition, the PFC controller is off resulting in a lower PFC bus voltage below 400 V.