ZHCSOY9 december 2021 UCC28781
PRODUCTION DATA
The VDD pin is the primary bias for the internal 5-V REF regulator, internal 13-V P13 regulator, other internal references, and the undervoltage lock-out (UVLO) circuit. As shown in Figure 7-5, the UVLO circuit connected to the VDD pin controls the internal power-path switches among VDD, P13, and SWS pins, in order to allow an external depletion-mode MOSFET (QS) to be able to perform both VVDD startup and switch-node voltage (VSW) sensing for ZVS control after startup. During startup, SWS and P13 pins are connected to VDD pin allowing QS to charge the VDD capacitor (CVDD) from the VSW.
After the VDD startup completes, the ZVS discriminator block and switching logic are enabled. Then, the transformer starts delivering energy to the output capacitor (CO) every switching cycle, so both output voltage (VO) and auxiliary winding voltage (VAUX) increase.
As VAUX is high enough, the auxiliary winding takes over to power VVDD. The UVLO circuit provides a turn-on threshold of VVDD(ON) at 17 V and turn-off threshold of VVDD(OFF) at 10.6 V. For fixed output voltage designs, the wide VVDD range can accommodate lower values of VDD capacitor (CVDD) and support shorter power-on delays.
For a fixed output voltage design, the rectified VAUX is directly connected to the VDD pin. As VVDD reaches VVDD(ON), the SWS pin is disconnected from the VDD pin by the internal power path switch, so the CVDD size has to be sufficient to hold VVDD higher than VVDD(OFF) until the positive auxiliary winding voltage is high enough to take over bias power delivery during VO soft start. Therefore, the calculation of minimum capacitance (CVDD(MIN)) needs to consider the discharging effect from the sink current of the UCC28781 during switching in its run state (IRUN(SW)), the average operating current of driver (IDR), and the average gate charge current of half-bridge FETs (IQg) throughout the longest duration of VO soft-start (tSS(MAX)) sequence.
tSS(MAX) estimation should consider the averaged soft-start current (ISEC(SS)) on the secondary side of the converter, load current on the output (IO(SS)) during start-up (if any), maximum output capacitance (CO(MAX)), and a 0.7-ms time-out potentially being triggered in the startup sequence. Include 1 ms in the equation to be the worst-case condition of the 0.7-ms timer.
During the VO soft-start sequence, VCST reaches the maximum current threshold on the CS pin (VCST(MAX)) , so ISEC(SS) at the minimum voltage of the input bulk capacitor (VBULK(MIN)) can be approximated as:
where