ZHCSOY9 december 2021 UCC28781
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Detailed Pin Description
- 7.3.1 BUR Pin (Programmable Burst Mode)
- 7.3.2 FB Pin (Feedback Pin)
- 7.3.3 REF Pin (Internal 5-V Bias)
- 7.3.4 VDD Pin (Device Bias Supply)
- 7.3.5 P13 and SWS Pins
- 7.3.6 S13 Pin
- 7.3.7 IPC Pin (Intelligent Power Control Pin)
- 7.3.8 RUN Pin (Driver and Bias Source for Isolator)
- 7.3.9 PWMH and AGND Pins
- 7.3.10 PWML and PGND Pins
- 7.3.11 SET Pin
- 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
- 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
- 7.3.14 XCD Pin
- 7.3.15 CS, VS, and FLT Pins
- 7.4
Device Functional Modes
- 7.4.1 Adaptive ZVS Control with Auto-Tuning
- 7.4.2 Dead-Time Optimization
- 7.4.3 EMI Dither and Dither Fading Function
- 7.4.4 Control Law Across Entire Load Range
- 7.4.5 Adaptive Amplitude Modulation (AAM)
- 7.4.6 Adaptive Burst Mode (ABM)
- 7.4.7 Low Power Mode (LPM)
- 7.4.8 First Standby Power Mode (SBP1)
- 7.4.9 Second Standby Power Mode (SBP2)
- 7.4.10 Startup Sequence
- 7.4.11 Survival Mode of VDD (INT_STOP)
- 7.4.12
System Fault Protections
- 7.4.12.1 Brown-In and Brown-Out
- 7.4.12.2 Output Over-Voltage Protection (OVP)
- 7.4.12.3 輸入過壓保護 (IOVP)
- 7.4.12.4 FLT 引腳上的過熱保護 (OTP)
- 7.4.12.5 CS 引腳上的過熱保護 (OTP)
- 7.4.12.6 可編程過功率保護 (OPP)
- 7.4.12.7 峰值功率限制 (PPL)
- 7.4.12.8 輸出短路保護 (SCP)
- 7.4.12.9 過流保護 (OCP)
- 7.4.12.10 External Shutdown
- 7.4.12.11 Internal Thermal Shutdown
- 7.4.13 Pin Open/Short Protections
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application Circuit
- 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
- 8.2.2 Detailed Design Procedure
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.4.12.2 Output Over-Voltage Protection (OVP)
The VS pin is used to sense the positive voltage level of the auxiliary winding voltage (VAUX) to detect an over-voltage condition of VO. When an OVP event is triggered, the auto-recovery version of OVP stops switching and there is a 1.5-s fault recovery time (tFDR) before any VO restart attempt is made. As QL turns off, the settled VAUX is equal to (VO+VF) x NAS, where NAS is the auxiliary-to-secondary turns ratio of the transformer, NA / NS, and VF is the forward voltage drop of the secondary-side rectifier. The VS pin senses VAUX through a voltage divider formed by RVS1 and RVS2. The pin voltage (VVS) is compared with an internal OVP threshold (VOVP). If VVS ≥ VOVP condition is qualified for three consecutive PWML pulses, the controller stops switching, brings RUN pin low, and initiates the 1.5-s time delay. During this long delay time, only the UVLO-cycle of VVDD is active, and there are no test pulses of PWML. After the 1.5-s timeout is completed and VVDD reaches the next VVDD(OFF), a normal start sequence begins. The calculation of RVS2 is
The long tFDR timer (1.5 s) helps to protect the power stage components from the large current stress during every restart and allows some time for VO to discharge in the case of light-load or no-load, before attempting restart.