Figure 7-1 shows a simplified flyback convertor with the main voltage regulation blocks of the device shown. The power train operation is the same as any DCM flyback circuit but accurate output voltage and current sensing is the key to primary-side control.

Figure 7-1 Simplified Flyback Convertor (with the main voltage regulation blocks)

In primary-side control, the output voltage is sensed on the auxiliary winding during the transfer of transformer energy to the secondary. As shown in Figure 7-2 it is clear there is a down slope representing a decreasing total rectifier V_F and resistance voltage drop (I_SR_S) as the secondary current decreases to zero. To achieve an accurate representation of the secondary output voltage on the auxiliary winding, the discriminator reliably blocks the leakage inductance reset and ringing, continuously samples the auxiliary voltage during the down slope after the ringing is diminished, and captures the error signal at the time the secondary winding reaches zero current. The internal reference on VS is 4.05 V; the resistor divider is selected as outlined in the VS pin description.

Figure 7-2 Auxiliary Winding Voltage

The UCC28700-Q1 VS signal sampler includes signal discrimination methods to ensure an accurate sample of the output voltage from the auxiliary winding. There are however some details of the auxiliary winding signal to ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any subsequent leakage inductance ring. Refer to Figure 7-3 for a detailed illustration of waveform criteria to ensure a reliable sample on the VS pin. The first detail to examine is the duration of the leakage inductance reset pedestal, T_{LK_RESET} in Figure 7-3. Because this can mimic the waveform of the secondary current decay, followed by a sharp downslope, it is important to keep the leakage reset time less than 500 ns for I_PRI minimum, and less than 1.5 μs for I_PRI maximum. The second detail is the amplitude of ringing on the V_AUX waveform following T_{LK_RESET}. The peak-to-peak voltage at the VS pin should be less than approximately 100 mV_p-p at least 200 ns before the end of the demagnetization time, t_DM. If there is a concern with excessive ringing, it usually occurs during light or no-load conditions, when t_DM is at the minimum. The tolerable ripple on VS is scaled up to the auxiliary winding voltage by R_S1 and R_S2, and is equal to 100 mV x (R_S1 + R_S2) / R_S2.

Figure 7-3 Auxiliary Waveform Details

During voltage regulation, the controller operates in frequency modulation mode and amplitude modulation mode as illustrated in Figure 7-4 below. The internal operating frequency limits of the device are 130 kHz maximum and 1 kHz minimum. The transformer primary inductance and primary peak current chosen sets the maximum operating frequency of the converter. The output preload resistor and efficiency at low power determines the converter minimum operating frequency. There is no stability compensation required for the UCC28700-Q1 controller.

Figure 7-4 Frequency and Amplitude Modulation Modes (during voltage regulation)