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ZHCSK35C March 2019 – March 2021 TPS92682-Q1

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

DAP|32
- MPDS380A
RHB|32
- MPQF130D
RHM|32
- MPQF152B

散熱焊盤機械數據 (封裝 | 引腳)

DAP|32
- PPTD363
RHB|32
- QFND644
RHM|32
- QFND588

訂購信息

7.3.16 Faults and Diagnostics

The TPS92682-Q1 includes a comprehensive configurable faults and diagnostics feature. Table 7-1 shows the list of the faults and diagnostics. A selected number of the faults (UVLO, RTOPEN, TW, TSD, and POR) are shared between the two channels.

As shown in Table 7-1, a selected number of the faults can be enabled or disabled using FLT EN-bits in the FEN1 and FEN2 registers. The rest of the faults and diagnostics feature are always enabled and operational.

All the faults and diagnostics features, except FBOPEN, TSD, and UVLO, have an associated Fault-Read-bit in the FLT1 and FLT2 registers. Upon occurrence of the fault, the associated Fault-Read-bit is set in the register map. Reading these registers clears the bits that are set if the condition no longer exists. The clearing of the Fault-Read-bits happens at the end of the SPI transfer read response, not at the end of the read command. Although FBOPEN fault does not have a dedicated Fault-Read-bit, this fault sets the OV-fault read bit.

In TPS92682-Q1, the OV, UV, ILIM, and OC faults can be configured to be a non-latched fault in the FLATEN Register. If a fault is configured as non-latched, upon occurrence of the fault, the associated channel turns off. The channel performs a soft start after expiration of a configurable fault timer and when the fault is cleared. In latched fault condition, the associated channel is turned off and remains off until the channel enable-bits are re-programmed in the EN Register.

Table 7-1 TPS92682 Faults and Diagnostics

LIST	DESCRIPTION	FAULT OR DIAGNOS.	FLT EN-BIT	FLT R-BIT	ENABLE FTIMER	F-PIN TRIGGER	DISABLE LATCH
OV	Output over voltage fault	Fault	Yes	Yes	No	Yes	Yes
UV	Output under voltage fault	Fault	Yes	Yes	Yes	Yes	Yes
ILIM	Cycle/Cycle switch current limit	Fault	Yes	Yes	Yes	Yes	Yes
UVLO	Input under voltage lockout	Fault	No	No	No	No	No
OC	ILED over current	Fault	Yes	Yes	Yes	Yes	Yes
UC	ILED under current	Diagnos.	No	Yes	No	No	No
ISNOPEN	ISNx open pin fault	Fault	Yes	Yes	No	Yes	No
RTOPEN	RT open pin fault	Fault	No	Yes	No	Yes	No
FBOPEN	FB pin open pin fault	Fault	Yes	No	No	Yes	No
TW	Thermal warning at 150°C (typ.)	Diagnos.	No	Yes	No	No	No
TSD	Thermal shutdown	Fault	No	No	No	Yes	No
POR	Power On Reset	Fault	No	Yes	No	Yes	No

As shown in Table 7-1, all faults, except UVLO, UC, and TW, set the active low fault pins, FLT1 and FLT2. Figure 7-14 shows the functionality of the fault pins. SYNC/ FLT2 is a dual function pin. When the SYNCEN bit in the EN Register is set to "1", SYNC/ FLT2 is an input pin and a square wave signal with the desired f_CLKM frequency must be applied to this pin. In this case, faults on both channels are ORed and applied to the FLT1 pin.

Figure 7-14 Fault PINs