ZHCSK35C March 2019 – March 2021 TPS92682-Q1
PRODUCTION DATA
Fault Enable-1 register, FEN1, determines which of the faults shown in Table 7-22 are enabled. If a fault enable is set to '1', it is enabled and it will affect the operation of the associated channel. The faults that are disabled will not affect the CHx fault pin output.
| ADDR | REGISTER | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DEFAULT |
|---|---|---|---|---|---|---|---|---|---|---|
| 13h | FEN1 | CH2RFEN | CH1RFEN | CH2FBOEN | CH1FBOEN | CH2OVEN | CH1OVEN | CH2UVEN | CH1UVEN | 00111100 |
0: Disables the CHxUV fault from affecting channel operation before or during the Soft-start ramp. In CV mode, CHx ILIM neither triggers the IFT, nor turns off the channel before or during the Soft-start ramp. Note that the cycle-by-cycle current limit is still active.
1: All the enabled faults are active before or during the Soft-start ramp.
If 2PH is set to '1', only CH1 parameter is used.