ZHCSIL4A June 2018 – December 2018 TPS51200A-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
10.1.1 LDO Design Guidelines
The minimum input to output voltage difference (headroom) decides the lowest usable supply voltage transconductance to drive a certain load. For device, a minimum of 300 mV (VLDOINMIIN – VOMAX) is needed to support a Gm driven sourcing current of 2 A based on a design of VIN = 3.3 V and COUT = 3 × 10 μF. Because the TPS51200A-Q1 device is essentially a Gm driven LDO, the impedance characteristics are both a function of the 1 / Gm and RDS(on) of the sourcing MOSFET (see Figure 33). The current inflection point of the design is between 2 A and 3 A. When ISRC is less than the inflection point, the LDO is considered to be operating in the Gm region; when ISRC is greater than the inflection point but less than the overcurrent limit point, the LDO is operating in the RDS(on) region. The maximum sourcing RDS(on) is 0.144 Ω with VIN = 3 V and TJ = 125°C.
Figure 33. Impedance Characteristics