ZHCSIL4A June 2018 – December 2018 TPS51200A-Q1
PRODUCTION DATA.
Use the information listed in Table 1 as the design parameters.
| PARAMETER | DDR | DDR2 | DR3 | LP DDR3 or DDR4 | ||
|---|---|---|---|---|---|---|
| FSB Data Rates | 200, 266, 333 and 400 MHz | 400, 533, 677 and 800 MHz | 800, 1066, 1330 and 1600 MHz | Same as DDR3 | ||
| Termination | Motherboard termination to VTT for all signals | On-die termination for data group. VTT termination for address, command and control signals | On-die termination for data group. VTT termination for address, command and control signals | Same as DDR3 | ||
| Termination Current Demand | Max source/sink transient currents of up to 2.6 A to 2.9 A | Not as demanding
|
Not as demanding
|
Same as DDR3 | ||
| Voltage Level | 2.5-V Core and I/O 1.25-V VTT | 1.8-V Core and I/O 0.9-V VTT | 1.5-V Core and I/O 0.75-V VTT | 1.2-V Core and I/O 0.6-V VTT | ||