ZHCSIL4A June 2018 – December 2018 TPS51200A-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
訂購信息
7.4.2 Tracking Startup and Shutdown
The TPS51200A-Q1 device also supports tracking startup and shutdown when the EN pin is tied directly to the system bus and not used to turn on or turn off the device. During tracking startup, the VO pin follows the REFOUT pin when the REFIN voltage is greater than 0.39 V. The REFIN pin follows the rise of the VDDQ rail though a voltage divider. The typical soft-start time for the VDDQ rail is approximately 3 ms, however this soft-star time can vary depending on the system configuration. The SS time of the VO output no longer depends on the OCL setting, but is a function of the SS time of the VDDQ rail. PGOOD is asserted 2 ms after the VO pin is within ±20% of the REFOUT pin. During tracking shutdown, the VO pin falls following the REFOUT pin until the REFOUT pin reaches 0.37 V. When the REFOUT pin falls below 0.37 V, the internal discharge MOSFETs are turned on and quickly discharge both the REFOUT and VO pins to GND. The PGOOD pin is deasserted when the VO pin is beyond the ±20% range of the REFOUT pin. Figure 20 shows the typical timing diagram for an application that uses tracking startup and shutdown.
Figure 19. Typical Timing Diagram for S3 and Pseudo-S5 Support 
Figure 20. Typical Timing Diagram of Tracking Startup and Shutdown