SPRS841E March 2012 – October 2019 TMS320C6652 , TMS320C6654
PRODUCTION DATA.
| HARDWARE FEATURES | TMS320C6652 | TMS320C6654 | |
|---|---|---|---|
| Frequency | MHz | 600 (0.6 GHz) | 850 (0.85 GHz) |
| Cycle Time | ns | 1.167 (0.6 GHz) | 1.175 (0.85 GHz) |
| MHz per core | 600 MHz | 750 MHz – 850 MHz | |
| Number of cores | 1 | 1 | |
| Max GMACs | 19.2 @ 600 MHz | 27.2 @ 800 MHz | |
| Max GFLOPs | 9.6 @ 600 MHz | 13.6 @ 800 MHz | |
| L1 KB per core | 32D / 32P | 32D / 32P | |
| L2 Dedicated per core | 1MB | 1MB | |
| L2 Shared | 0MB | 0MB | |
| DDR (with ECC) MHz | 32b 1066 MHz | 32b 1066 MHz | |
| Coprocessors | — | — | |
| Peripheral | DDR3 Memory Controller (32-bit bus width) [1.5 V I/O] (clock source = DDRREFCLKN|P) | 1 | |
| DDR3 Maximum Data Rate | 1066 | ||
| EDMA3 (64 independent channels) [DSP/3 clock rate] | 1 | ||
| PCIe (two lanes) | — | 1 | |
| 10/100/1000 EMAC | — | 1 × SGMII | |
| Management Data Input/Output (MDIO) | — | 1 | |
| EMIF16 | 1 | ||
| McBSP | 2 | ||
| SPI | 1 | ||
| UART | 2 | ||
| uPP | 1 | ||
| uPP / EMIF16 (muxed) | Yes | Yes | |
| I2C | 1 | ||
| 64-Bit Timers (configurable) (internal clock source = CPU/6 clock frequency) | 8 (each configurable as two 32-bit timers) | ||
| General-Purpose Input/Output port (GPIO) | 32 | ||
| 2x PLLs | Yes | Yes | |
| On-Chip Memory | CorePac Memory | 32KB L1 Program Memory [SRAM/Cache]
32KB L1 Data Memory [SRAM/Cache] 1024KB L2 Unified Memory/Cache |
|
| ROM Memory | 128KB L3 ROM | ||
| C66x CorePac
Revision ID |
CorePac Revision ID Register
(address location: 0181 2000h) |
See Section 7.5. | |
| JTAG BSDL_ID | JTAGID register (address location: 0262 0018h) | See Section 8.3.3. | |
| Extended Case Temp | –40ºC to 100ºC | –40ºC to 100ºC | |
| Voltage | Core (V) | SmartReflex™ variable supply | |
| I/O (V) | 1.0 V, 1.5 V, and 1.8 V | ||
| Process Technology | µm | 0.040 µm | |
| BGA Package | 21 mm × 21 mm, 0.80 mm pitch | 625-Pin Flip-Chip Plastic BGA (CZH or GZH) | |
| Product Status(1) | Production Data (PD) | PD | PD |