ZHCSE15F July 2015 – May 2018 SN65DP159 , SN75DP159
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VOH | Single-ended high level output voltage | Data rate ≤ 1.65-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; DR = 750-Mbps, VSadj = 7.06-kΩ | VCC – 10 | VCC + 10 | mV | |
| 1.65-Gbps < Data rate ≤ 3.4-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; DR = 2.97-Gbps, VSadj = 7.06-kΩ | VCC – 200 | VCC + 10 | ||||
| VOH | Single-ended high level output voltage | 3.4-Gbps < Data rate < 6 Gbps; PRE_SEL = NC; TX_TERM_CTL = L; SLEW_CTL = H; OE = H; DR = 6-Gbps, VSadj = 7.06-kΩ | VCC – 400 | VCC + 10 | mV | |
| VOL | Single-ended low level output voltage | Data rate ≤ 1.65-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; DR = 750-Mbps, VSadj = 7.06-kΩ | VCC – 600 | VCC – 400 | mV | |
| 1.65-Gbps < Data rate ≤ 3.4-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; DR = 2.97-Gbps, VSadj = 7.06-kΩ | VCC – 700 | VCC – 400 | ||||
| VOL | Single-ended low level output voltage | 3.4-Gbps < Data rate < 6-Gbps; PRE_SEL = NC; TX_TERM_CTL = L; SLEW_CTL = H; OE = H; DR = 6-Gbps | VCC – 1000 | VCC – 400 | mV | |
| VSWING_DA | Single-ended output voltage swing on data lane | PRE_SEL = NC; TX_TERM_CTL = H/NC/L; SLEW_CTL = H; OE = H; DR = 270-Mbs/2.97/6Gbps VSadj = 7.06-kΩ | 400 | 500 | 600 | mV |
| VSWING_CLK | Single-ended output voltage swing on clock lane | Data rate ≤ 3.4-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; VSadj = 7.06-kΩ | 400 | 500 | 600 | mV |
| Data rate > 3.4-Gbps; PRE_SEL = NC; TX_TERM_CTL = NC; SLEW_CTL = H; OE = H; VSadj = 7.06-kΩ | 200 | 300 | 400 | |||
| ΔVSWING | Change in single-end output voltage swing per 100 Ω ΔVsadj | 20 | mV | |||
| ΔVOCM(SS) | Change in steady state output common mode voltage between logic levels | –5 | 5 | mV | ||
| VOD(PP) | Output differential voltage before pre-emphasis | Vsadj = 7.06-kΩ; PRE_SEL = Z, See Figure 8 | 800 | 1200 | mV | |
| VOD(SS) | Steady-state output differential voltage | Vsadj = 7.06-kΩ; PRE_SEL = L, See Figure 9 | 600 | 1050 | mV | |
| ILEAK | Failsafe condition leakage current | VCC = 0-V; VDD = 0-V; output pulled to 3.3 V through 50-Ω resistors | 45 | µA | ||
| IOS | Short circuit current limit | Main link output shorted to GND | 50 | mA | ||
| RTERM | Source termination resistance for HDMI 2.0 | 75 | 150 | Ω | ||