ZHCSE15F July 2015 – May 2018 SN65DP159 , SN75DP159
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| DR_RX_DATA | Ddata lanes data rate | 0.25 | 6 | Gbps | ||
| DR_RX_CLK | Clock lanes clock rate | 25 | 340 | MHz | ||
| tRX_DUTY | Input clock duty circle | 40% | 50% | 60% | ||
| tCLK_JIT | Input clock jitter tolerance | 0.3 | Tbit | |||
| tDATA_JIT | Input data jitter tolerance | Test the TTP2, see Figure 10 | 150 | ps | ||
| TRX_INTRA | Input intra-pair skew tolerance | Test at TTP2 when DR = 1.6-Gbps, see Figure 10 | 112 | ps | ||
| TRX_INTER | Input inter-pair skew tolerance | 1.8 | ns | |||
| EQH(D) | Fixed EQ gain for data lane IN_D(0,1,2)n/p | EQ_SEL/A0 = H; Fixed EQ gain,
test at 6-Gbps |
15 | dB | ||
| EQL(D) | Fixed EQ gain for data lane IN_D(0,1,2)n/p | EQ_SEL/A0 = L; Fixed EQ gain,
test at 6-Gbps |
7.5 | dB | ||
| EQZ(D) | Adaptive EQ gain for data lane IN_D(0,1,2)n/p | EQ_SEL/A0 = Z; adaptive EQ | 2 | 15 | dB | |
| EQ(c) | EQ gain for clock lane IN_CLKn/p | EQ_SEL/A0 = H,L,NC | 3 | |||
| RINT | Input differential termination impedance | 80 | 100 | 120 | Ω | |
| VITERM | Input termination voltage | OE = H | 0.7 | V | ||
| VID_PP | Input differential voltage (peak to peak) | Tested at TTP2, check Figure 10 | 75 | 1200 | mVPP | |