SLLSFV1 March 2025 MCF8329A-Q1
PRODUCTION DATA
MCF8329A-Q1 uses buffers internally to store the data received on I2C. Highest priority is given to collecting data on the I2C Bus. There are 2 buffers (ping-pong) for I2C Rx Data and 2 buffers (ping-pong) for I2C Tx Data.
A write request from external MCU is stored in Rx Buffer 1 and then the parsing block is triggered to work on this data in Rx Buffer 1. While MCF8329A-Q1 is processing a write packet from Rx Buffer 1, if there is another new read/write request, the entire data from the I2C bus is stored in Rx Buffer 2 and it will be processed after the current request.
MCF8329A-Q1 can accommodate a maximum of two consecutive read/write requests. If MCF8329A-Q1 is busy due to high priority interrupts, the data sent will be stored in internal buffers (Rx Buffer 1 and Rx Buffer 2). At this point, if there is a third read/write request, the Target ID will be NACK’d as the buffers are already full.
During read operations, the read request is processed and the read data from the register is stored in the Tx Buffer along with the CRC byte, if enabled. Now if the external MCU initiates an I2C Read (Target ID + R bit), the data from this Tx Buffer is sent over I2C. Since there are two Tx Buffers, register data from 2 MCF8329A-Q1 reads can be buffered. Given this scenario, if there is a third read request, the control word will be stored in the Rx Buffer 1, but it will not be processed by MCF8329A-Q1 as the Tx Buffers are full.
Once a data is read from Tx Buffer, the data is no longer stored in the Tx buffer. The buffer is cleared and it becomes available for the next data to be stored. If the read transaction was interrupted in between and if the MCU had not read all the bytes, external MCU can initiate another I2C read (only I2C read, without any control word information) to read all the data bytes from first.