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SLLSFV1 March 2025 MCF8329A-Q1

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RRY|32
- MPQF713A

散熱焊盤機械數據 (封裝 | 引腳)

RRY|32
- QFND763

訂購信息

sllsfv1_oa

6.3.23 Protections

The MCF8329A-Q1 is protected from a host of fault events including motor lock, PVDD undervoltage, AVDD undervoltage, GVDD undervoltage, bootstrap undervoltage, overtemperature and overcurrent events. Table 6-5 summarizes the response, recovery modes, gate driver status, reporting mechanism for different faults.

Note:

Actionable and report only faults (latched or retry) are always reported on nFAULT pin (as logic low).
Priority order for multi-fault scenarios is latched > slower retry time fault > faster retry time fault > report only fault. For example, if a latched and retry fault happen simultaneously, the device stays latched in fault mode until user issues clear fault command by writing 1b to CLR_FLT or through a power recycle. If two retry faults with different retry times happen simultaneously, the device retries only after the longer (slower) retry time lapses.
Recovery refers only to state of gate driver after the fault condition is removed. Automatic indicates that the device automatically recovers (and gate driver outputs and hence external FETs are active) when retry time lapses after the fault condition is removed. Latched indicates that the device waits for clearing of fault condition (by writing 1b to CLR_FLT bit) or through a power recycle.
The GVDD undervoltage, BST under voltage, VDS OCP, SENSE OCP faults can take up to 200ms after fault response (gate driver outputs pulled low to put the external FETs in Hi-Z) to be reported on nFAULT pin (as logic low).
Latched faults can take up to 200ms after CLR_FLT command is issued (over I²C) to be cleared.
CLR_FLT command (over I²C) can clear all the faults including latched, retry and auto recovery faults.

Table 6-5 Fault Action and Response

FAULT	CONDITION	CONFIGURATION	REPORT	GATE DRIVER	LOGIC	RECOVERY
PVDD under-voltage (PVDD_UV)	V_PVDD < V_{PVDD_UV}	—	nFAULT	Disabled	Disabled	Automatic: V_PVDD > V_{PVDD_UV}
AVDD POR (AVDD_POR)	V_AVDD < V_{AVDD_POR}	—	nFAULT	Disabled	Disabled	Automatic: V_AVDD > V_{AVDD_POR}
GVDD under-voltage (GVDD_UV)	V_GVDD < V_{GVDD_UV}	GVDD_UV_MODE = 0b	nFAULT and GATE_DRIVER_FAULT_STATUS Register	Pulled Low ^⁽¹⁾	Active	Latched: CLR_FLT
GVDD under-voltage (GVDD_UV)	V_GVDD < V_{GVDD_UV}	GVDD_UV_MODE = 1b	nFAULT and GATE_DRIVER_FAULT_STATUS Register	Pulled Low ^⁽¹⁾	Active	Retry: t_{LCK_RETRY}
BSTx under-voltage (BST_UV)	V_BSTx - V_SHx < V_{BST_UV}	DIS_BST_FLT = 0b BST_UV_MODE = 0b	nFAULT and GATE_DRIVER_FAULT_STATUS Register	Pulled Low ^⁽¹⁾	Active	Latched: CLR_FLT
BSTx under-voltage (BST_UV)	V_BSTx - V_SHx < V_{BST_UV}	DIS_BST_FLT = 0b BST_UV_MODE = 1b	nFAULT and GATE_DRIVER_FAULT_STATUS Register	Pulled Low ^⁽¹⁾	Active	Retry: t_{LCK_RETRY}
V_DS overcurrent (VDS_OCP)	V_DS > V_{SEL_VDS_LVL}	DIS_VDS_FLT = 0b VDS_FLT_MODE = 0b	nFAULT and GATE_DRIVER_FAULT_STATUS Register	Pulled Low ^⁽¹⁾	Active	Latched: CLR_FLT
V_DS overcurrent (VDS_OCP)	V_DS > V_{SEL_VDS_LVL}	DIS_VDS_FLT = 0b VDS_FLT_MODE = 1b	nFAULT and GATE_DRIVER_FAULT_STATUS Register	Pulled Low ^⁽¹⁾	Active	Retry: t_{LCK_RETRY}
V_SENSE overcurrent (SEN_OCP)V_SENSE overcurrent (SEN_OCP)	V_SP > V_{SENSE_LVL}	DIS_SNS_FLT = 0b SNS_FLT_MODE = 0b	nFAULT and GATE_DRIVER_FAULT_STATUS Register	Pulled Low ^⁽¹⁾	Active	Latched: CLR_FLT
V_SENSE overcurrent (SEN_OCP)V_SENSE overcurrent (SEN_OCP)	V_SP > V_{SENSE_LVL}	DIS_SNS_FLT = 0b SNS_FLT_MODE = 1b	nFAULT and GATE_DRIVER_FAULT_STATUS Register	Pulled Low ^⁽¹⁾	Active	Retry: t_{LCK_RETRY}
3 Motor Lock (MTR_LCK )	Motor lock: Abnormal Speed; No Motor Lock; Abnormal BEMF	MTR_LCK_MODE = 0000b or 0001b	nFAULT and CONTROLLER_FAULT_STATUS register	Pulled Low ^⁽¹⁾(MOSFETs in Hi-Z)	Active	Latched: CLR_FLT
		MTR_LCK_MODE = 0010b or 0011b	nFAULT and CONTROLLER_FAULT_STATUS register	Low side brake logic	Active	Latched: CLR_FLT
		MTR_LCK_MODE = 0100b or 0101b	nFAULT and CONTROLLER_FAULT_STATUS register	Pulled Low ^⁽¹⁾(MOSFETs in Hi-Z)	Active	Retry: t_{LCK_RETRY}
		MTR_LCK_MODE = 0110b or 0111b	nFAULT and CONTROLLER_FAULT_STATUS register	Low side brake logic	Active	Retry: t_{LCK_RETRY}
		MTR_LCK_MODE = 1000b	nFAULT and CONTROLLER_FAULT_STATUS register	Active	Active	No action
		MTR_LCK_MODE = 1001b to 1111b	None	Active	Active	No action
Hardware Lock-Detection Current Limit (HW_LOCK_ILIMIT)	Phase Current > HW_LOCK_ILIMIT	HW_LOCK_ILIMIT_MODE = 0000b or 0001b	nFAULT and CONTROLLER_FAULT_STATUS register	Pulled Low ^⁽¹⁾(MOSFETs in Hi-Z)	Active	Latched: CLR_FLT
		HW_LOCK_ILIMIT_MODE =0010b or 0011b	nFAULT and CONTROLLER_FAULT_STATUS register	Low-side brake logic	Active	Latched: CLR_FLT
		HW_LOCK_ILIMIT_MODE = 0100b or 0101b	nFAULT and CONTROLLER_FAULT_STATUS register	Pulled Low ^⁽¹⁾(MOSFETs in Hi-Z)	Active	Retry: t_{LCK_RETRY}
		HW_LOCK_ILIMIT_MODE = 0110b or 0111b	nFAULT and CONTROLLER_FAULT_STATUS register	Low-side brake logic	Active	Retry: t_{LCK_RETRY}
		HW_LOCK_ILIMIT_MODE= 1000b	nFAULT and CONTROLLER_FAULT_STATUS register	Active	Active	No action
		HW_LOCK_ILIMIT_MODE = 1001b to 1111b	None	Active	Active	No action
ADC based Lock-Detection Current Limit (LOCK_ILIMIT)	Phase Current > LOCK_ILIMIT	LOCK_ILIMIT_MODE = 0000b or 0001b	nFAULT and CONTROLLER_FAULT_STATUS register	Pulled Low ^⁽¹⁾(MOSFETs in Hi-Z)	Active	Latched: CLR_FLT
		LOCK_ILIMIT_MODE = 0010b or 0011b	nFAULT and CONTROLLER_FAULT_STATUS register	Low-side brake logic	Active	Latched: CLR_FLT
		LOCK_ILIMIT_MODE = 0100b or 0101b	nFAULT and CONTROLLER_FAULT_STATUS register	Pulled Low ^⁽¹⁾(MOSFETs in Hi-Z)	Active	Retry: t_{LCK_RETRY}
		LOCK_ILIMIT_MODE = 0110b or 0111b	nFAULT and CONTROLLER_FAULT_STATUS register	Low-side brake logic	Active	Retry: t_{LCK_RETRY}
		LOCK_ILIMIT_MODE= 1000b	nFAULT and CONTROLLER_FAULT_STATUS register	Active	Active	No action
		LOCK_ILIMIT_MODE = 1001b to 1111b	None	Active	Active	No action
IPD Timeout Fault (IPD_T1_FAULT)	IPD TIME > 500ms (approx), during IPD current ramp up or ramp down	IPD_TIMEOUT_FAULT_EN = 0b	-	Active	Active	No action
IPD Timeout Fault (IPD_T1_FAULT)		IPD_TIMEOUT_FAULT_EN = 1b	nFAULT and CONTROLLER_FAULT_STATUS register	Pulled Low ^⁽¹⁾(MOSFETs in Hi-Z)	Active	Retry: t_{LCK_RETRY}
IPD Frequency Fault (IPD_FREQ_FAULT)	IPD pulse before the current decay in previous IPD	IPD_FREQ_FAULT_EN = 0b	-	Active	Active	No action
IPD Frequency Fault (IPD_FREQ_FAULT)	IPD pulse before the current decay in previous IPD	IPD_FREQ_FAULT_EN = 1b	nFAULT and CONTROLLER_FAULT_STATUS register	Pulled Low ^⁽¹⁾(MOSFETs in Hi-Z)	Active	Retry: t_{LCK_RETRY}
MPET Back-EMF Fault (MPET_BEMF_FAULT)	Motor Back EMF < STAT_DETECT_THR	MPET_CMD = 1 or MPET_KE = 1	nFAULT and CONTROLLER_FAULT_STATUS register	Hi-Z	Active	Latched: CLR_FLT
Maximum V_PVDD (over-voltage) fault	V_PVDD > MAX_VM_MOTOR, if MAX_VM_MOTOR ≠ 000b	MAX_VM_MODE = 0b	nFAULT and CONTROLLER_FAULT_STATUS register	Pulled Low ^⁽¹⁾(MOSFETs in Hi-Z)	Active	Latched: CLR_FLT
Maximum V_PVDD (over-voltage) fault	V_PVDD > MAX_VM_MOTOR, if MAX_VM_MOTOR ≠ 000b	MAX_VM_MODE = 1b	nFAULT and CONTROLLER_FAULT_STATUS register	Pulled Low ^⁽¹⁾(MOSFETs in Hi-Z)	Active	Automatic: (V_VM < MAX_VM_MOTOR - VM_UV_OV_HYS) V
Minimum V_PVDD (under-voltage) fault	V_PVDD < MIN_VM_MOTOR, if MIN_VM_MOTOR ≠ 000b	MIN_VM_MODE = 0b	nFAULT and CONTROLLER_FAULT_STATUS register	Pulled Low ^⁽¹⁾(MOSFETs in Hi-Z)	Active	Latched: CLR_FLT
Minimum V_PVDD (under-voltage) fault	V_PVDD < MIN_VM_MOTOR, if MIN_VM_MOTOR ≠ 000b	MIN_VM_MODE = 1b	nFAULT and CONTROLLER_FAULT_STATUS register	Pulled Low ^⁽¹⁾(MOSFETs in Hi-Z)	Active	Automatic: (V_VM > MIN_VM_MOTOR + VM_UV_OV_HYS) V
Bus Current Limit	I_VM > BUS_CURRENT_LIMIT	BUS_CURRENT_LIMIT_ENABLE = 1b	nFAULT and CONTROLLER_FAULT_STATUS register	Active; motor speed/power/current will be restricted to limit DC bus current	Active	Automatic: Restriction is removed when I_VM < BUS_CURRENT_LIMIT
Current Loop Saturation	Indication of current loop saturation due to lower V_VM	SATURATION_FLAGS_EN = 1b	nFAULT and CONTROLLER_FAULT_STATUS register	Active; motor speed/power/current may not reach reference	Active	Automatic: motor will reach reference operating point upon exiting saturation
Speed/power Loop Saturation	Indication of speed/power loop saturation due to lower V_VM, lower ILIMIT setting etc.,	SATURATION_FLAGS_EN = 1b	nFAULT and CONTROLLER_FAULT_STATUS register	Active; motor speed/power may not reach reference	Active	Automatic: motor will reach reference operating point upon exiting saturation
External Watchdog Fault	Time between watchdog tickles > EXT_WD_CONFIG	EXT_WD_EN = 1bEXT_WD_FAULT_MODE = 0b	nFAULT and CONTROLLER_FA ULT_STATUS register	Active	Active	No action
External Watchdog Fault	Time between watchdog tickles > EXT_WD_CONFIG	EXT_WD_EN = 1bEXT_WD_FAULT_MODE = 1b	nFAULT and CONTROLLER_FA ULT_STATUS register	Pulled Low (MOSFETs in Hi-Z) ^⁽¹⁾	Active	Latched: CLR_FLT
Thermal shutdown (TSD)	T_J > T_TSD	OTS_AUTO_RECOVERY = 0b	nFAULT and GATE_DRIVER_FAULT_STATUS Register	Pulled Low (MOSFETs in Hi-Z) ^⁽¹⁾	Active	Latched: CLR_FLT
Thermal shutdown (TSD)	T_J > T_TSD	OTS_AUTO_RECOVERY = 1b	nFAULT and GATE_DRIVER_FAULT_STATUS Register	Pulled Low (MOSFETs in Hi-Z) ^⁽¹⁾	Active	Automatic: T_J < T_OTSD – T_HYS

(1) Pulled Low: GHx and GLx are actively pulled low by the gate driver

Note: Any fault reporting on nFAULT pin or CONTROLLER_FAULT_STATUS register or GATE_DRIVER_FAULT_STATUS register can have a latency up to 200ms.