SLLSFV1 March 2025 MCF8329A-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Three Phase BLDC Gate Drivers
- 6.3.2 Gate Drive Architecture
- 6.3.3 AVDD Linear Voltage Regulator
- 6.3.4 Low-Side Current Sense Amplifier
- 6.3.5 Device Interface Modes
- 6.3.6 Motor Control Input Options
- 6.3.7 Bootstrap Capacitor Initial Charging
- 6.3.8 Starting the Motor Under Different Initial Conditions
- 6.3.9 Motor Start Sequence (MSS)
- 6.3.10 Closed Loop Operation
- 6.3.11 Maximum Torque Per Ampere (MTPA) Control
- 6.3.12 Flux Weakening Control
- 6.3.13 Motor Parameters
- 6.3.14 Motor Parameter Extraction Tool (MPET)
- 6.3.15 Anti-Voltage Surge (AVS)
- 6.3.16 Active Braking
- 6.3.17 Output PWM Switching Frequency
- 6.3.18 Dead Time Compensation
- 6.3.19 Voltage Sense Scaling
- 6.3.20 Motor Stop Options
- 6.3.21 FG Configuration
- 6.3.22 DC Bus Current Limit
- 6.3.23
Protections
- 6.3.23.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
- 6.3.23.2 AVDD Power on Reset (AVDD_POR)
- 6.3.23.3 GVDD Undervoltage Lockout (GVDD_UV)
- 6.3.23.4 BST Undervoltage Lockout (BST_UV)
- 6.3.23.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 6.3.23.6 VSENSE Overcurrent Protection (SEN_OCP)
- 6.3.23.7 Thermal Shutdown (OTSD)
- 6.3.23.8 Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
- 6.3.23.9 Lock Detection Current Limit (LOCK_ILIMIT)
- 6.3.23.10 Motor Lock (MTR_LCK)
- 6.3.23.11 Motor Lock Detection
- 6.3.23.12 MPET Faults
- 6.3.23.13 IPD Faults
- 6.4 Device Functional Modes
- 6.5 External Interface
- 6.6 EEPROM access and I2C interface
- 7 EEPROM (Non-Volatile) Register Map
- 8 RAM (Volatile) Register Map
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RRY|32
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RRY|32
訂購(gòu)信息
6.3.22 DC Bus Current Limit
The DC bus current limit feature can be used in applications to limit the current supplied by source without entering the constant current mode. The DC bus current limit feature can be enabled by setting BUS_CURRENT_LIMIT_ENABLE to 1b. The DC bus current limit threshold can be configured using BUS_CURRENT_LIMIT. The DC bus current limit limits the speed reference and a functional diagram is shown in Figure 6-43, Figure 6-44 and Figure 6-45. Enabling this feature may restrict the speed of the motor so that current drawn from source is limited. The algorithm estimates the bus current using the measured phase currents, phase voltage and DC bus voltage. The current limit status is reported on BUS_CURRENT_LIMIT_STATUS.
Figure 6-43 DC Bus Current Limit Functional Block Diagram in Speed or Power Control
Mode
Figure 6-44 DC Bus Current Limit Functional Block Diagram in Current Control Mode
Figure 6-45 DC Bus Current Limit Functional Block Diagram in Modulation Index Control
Mode- DC bus current limit feature is not available when active braking is enabled.
- MCF8329A-Q1 implements a 5% hysteresis around BUS_CURRENT_LIMIT to avoid chattering around this set-point.