SLLSFV1 March 2025 MCF8329A-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Three Phase BLDC Gate Drivers
- 6.3.2 Gate Drive Architecture
- 6.3.3 AVDD Linear Voltage Regulator
- 6.3.4 Low-Side Current Sense Amplifier
- 6.3.5 Device Interface Modes
- 6.3.6 Motor Control Input Options
- 6.3.7 Bootstrap Capacitor Initial Charging
- 6.3.8 Starting the Motor Under Different Initial Conditions
- 6.3.9 Motor Start Sequence (MSS)
- 6.3.10 Closed Loop Operation
- 6.3.11 Maximum Torque Per Ampere (MTPA) Control
- 6.3.12 Flux Weakening Control
- 6.3.13 Motor Parameters
- 6.3.14 Motor Parameter Extraction Tool (MPET)
- 6.3.15 Anti-Voltage Surge (AVS)
- 6.3.16 Active Braking
- 6.3.17 Output PWM Switching Frequency
- 6.3.18 Dead Time Compensation
- 6.3.19 Voltage Sense Scaling
- 6.3.20 Motor Stop Options
- 6.3.21 FG Configuration
- 6.3.22 DC Bus Current Limit
- 6.3.23
Protections
- 6.3.23.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
- 6.3.23.2 AVDD Power on Reset (AVDD_POR)
- 6.3.23.3 GVDD Undervoltage Lockout (GVDD_UV)
- 6.3.23.4 BST Undervoltage Lockout (BST_UV)
- 6.3.23.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 6.3.23.6 VSENSE Overcurrent Protection (SEN_OCP)
- 6.3.23.7 Thermal Shutdown (OTSD)
- 6.3.23.8 Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
- 6.3.23.9 Lock Detection Current Limit (LOCK_ILIMIT)
- 6.3.23.10 Motor Lock (MTR_LCK)
- 6.3.23.11 Motor Lock Detection
- 6.3.23.12 MPET Faults
- 6.3.23.13 IPD Faults
- 6.4 Device Functional Modes
- 6.5 External Interface
- 6.6 EEPROM access and I2C interface
- 7 EEPROM (Non-Volatile) Register Map
- 8 RAM (Volatile) Register Map
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
4 Pin Configuration and Functions
Figure 4-1 MCF8329A-Q132-Pin WQFN With Exposed Thermal PadTop
ViewTable 4-1 Pin Functions
| PIN | 32-pin package | TYPE(1) | DESCRIPTION | |
|---|---|---|---|---|
| NAME | MCF8329A-Q1 | |||
| AGND | 23 | GND | Device analog ground | |
| AVDD | 24 | PWR | 3.3V regulator output. Connect a X7R, 1μF or 2.2μF, 10V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 50mA for external circuits. AVDD capacitor should have an effective capacitance between 0.5μF and 2.8μF after operating voltage (AVDD) and temperature derating. | |
| BSTA | 7 | O | Bootstrap output pin. Connect a X7R, 1μF, 25V ceramic capacitor between BSTA and SHA. | |
| BSTB | 11 | O | Bootstrap output pin. Connect a X7R, 1μF, 25V ceramic capacitor between BSTB and SHB. | |
| BSTC | 15 | O | Bootstrap output pin. Connect a X7R, 1μF, 25V ceramic capacitor between BSTC and SHC. | |
| CPH | 5 | PWR | Charge pump switching node. Connect a X7R, PVDD-rated ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin. | |
| CPL | 4 | PWR | ||
| DGND | 1 | GND | Device digital ground | |
| DIR | 29 | I | Direction of motor
spinning; When low, phase driving sequence is OUT A → OUT B → OUT C When high, phase driving sequence is OUT A → OUT C → OUT B Connect to GND if not used |
|
| DRVOFF | 22 | I | Independent driver shutdown path. Pulling DRVOFF high turns off all external MOSFETs by putting the gate drivers into the pull-down state. This signal bypasses and overrides the digital and control core. | |
| DVDD | 32 | PWR | 1.5V internal regulator output. Connect a X7R, 1 or 2.2μF,10V ceramic capacitor between the DVDD and DGND pins. DVDD capacitor should have an effective capacitance between 0.5μF and 2.8μF after operating voltage (DVDD) and temperature derating. | |
| EXT_CLK | 30 | I | External clock reference input in external clock reference mode. | |
| FG | 26 | O | Motor speed indicator output. Open-drain output requires an external pull-up resistor to 1.8 to 5V. External pull up resistor needs to be connected even if the pin functionality is not used. | |
| GHA | 9 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET | |
| GHB | 13 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET | |
| GHC | 17 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET | |
| GLA | 10 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET | |
| GLB | 14 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET | |
| GLC | 18 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET | |
| GND | 2 | GND | Device power ground | |
| GVDD | 6 | PWR | Gate driver power supply output. Connect a X7R, 30V rated ceramic ≥ 10μF local capacitance between the GVDD and GND pins. TI recommends a capacitor value of >10x CBSTx and voltage rating at least twice the normal operating voltage of the pin. | |
| LSS | 19 | PWR | Low side source pin, connect all sources of the external low-side MOSFETs here. This pin is the sink path for the low-side gate driver, and serves as an input to monitor the low-side MOSFET VDS voltage and VSEN_OCP voltage. | |
| nFAULT | 31 | O | Fault indicator. This pin is pulled logic-low with fault condition. Open-drain output requires an external pull-up resistor to 1.8V to 5 V. External pull up resistor needs to be connected even if the pin functionality is not used. | |
| PVDD | 3 | PWR | Gate driver power supply input. Connect to the bridge power supply. Connect a X7R, 0.1μF, >2x PVDD-rated ceramic and >10μF local capacitance between the PVDD and GND pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin. | |
| SCL | 28 | I | I2C clock input | |
| SDA | 27 | I/O | I2C data line | |
| SHA | 8 | I/O | High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink. | |
| SHB | 12 | I/O | High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink. | |
| SHC | 16 | I/O | High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink. | |
| SN | 21 | I | Current sense amplifier input. Connect to the low-side of the current shunt resistor. | |
| SP | 20 | I | Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. | |
| SPEED/WAKE | 25 | I | Multifunction input.
Device sleep/wake input. Device speed input; supports analog, PWM or frequency based reference (speed or current or power or voltage) input. |
|
| Thermal pad | - | PWR | Must be connected to ground | |
(1) I = input, O = output, GND = ground pin, PWR = power, NC = no connect