ZHCSH29B April 2017 – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1
PRODUCTION DATA.
Address: 0x2B
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| PLL_MODE[1:0] | Reserved | EXT_CLK_FREQ[4:0] | |||||
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7:6 | PLL_MODE[1:0] | R/W | 0x2* | Selection of external clock and PLL operation:
0x0 - Forced to internal RC oscillator — PLL disabled. 0x1 - PLL is enabled in STANDBY and ACTIVE modes. Automatic external clock use when available, interrupt generated if external clock appears or disappears. 0x2 - PLL is enabled only in ACTIVE mode. Automatic external clock use when available, interrupt generated if external clock appears or disappears. 0x3 - Reserved |
| 5 | Reserved | R/W | 0 | |
| 4:0 | EXT_CLK_FREQ[4:0] | R/W | 0x01* | Frequency of the external clock (CLKIN):
0x00 - 1 MHz 0x01 - 2 MHz 0x02 - 3 MHz ... 0x16 - 23 MHz 0x17 - 24 MHz 0x18...0x1F - Reserved See Specifications for input clock frequency tolerance. |