ZHCSH29B April 2017 – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Descriptions
- 7.3.1 DC-DC Converters
- 7.3.2 Sync Clock Functionality
- 7.3.3 Power-Up
- 7.3.4 Regulator Control
- 7.3.5 Enable and Disable Sequences
- 7.3.6 Device Reset Scenarios
- 7.3.7 Diagnosis and Protection Features
- 7.3.8 GPIO Signal Operation
- 7.3.9 Digital Signal Filtering
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1
Register Descriptions
- 7.6.1.1 OTP_REV
- 7.6.1.2 BUCK0_CTRL1
- 7.6.1.3 BUCK1_CTRL1
- 7.6.1.4 BUCK2_CTRL1
- 7.6.1.5 BUCK3_CTRL1
- 7.6.1.6 BUCK0_VOUT
- 7.6.1.7 BUCK0_FLOOR_VOUT
- 7.6.1.8 BUCK1_VOUT
- 7.6.1.9 BUCK1_FLOOR_VOUT
- 7.6.1.10 BUCK2_VOUT
- 7.6.1.11 BUCK2_FLOOR_VOUT
- 7.6.1.12 BUCK3_VOUT
- 7.6.1.13 BUCK3_FLOOR_VOUT
- 7.6.1.14 BUCK0_DELAY
- 7.6.1.15 BUCK1_DELAY
- 7.6.1.16 BUCK2_DELAY
- 7.6.1.17 BUCK3_DELAY
- 7.6.1.18 GPIO2_DELAY
- 7.6.1.19 GPIO3_DELAY
- 7.6.1.20 RESET
- 7.6.1.21 CONFIG
- 7.6.1.22 INT_TOP1
- 7.6.1.23 INT_TOP2
- 7.6.1.24 INT_BUCK_0_1
- 7.6.1.25 INT_BUCK_2_3
- 7.6.1.26 TOP_STAT
- 7.6.1.27 BUCK_0_1_STAT
- 7.6.1.28 BUCK_2_3_STAT
- 7.6.1.29 TOP_MASK1
- 7.6.1.30 TOP_MASK2
- 7.6.1.31 BUCK_0_1_MASK
- 7.6.1.32 BUCK_2_3_MASK
- 7.6.1.33 SEL_I_LOAD
- 7.6.1.34 I_LOAD_2
- 7.6.1.35 I_LOAD_1
- 7.6.1.36 PGOOD_CTRL1
- 7.6.1.37 PGOOD_CTRL2
- 7.6.1.38 PGOOD_FLT
- 7.6.1.39 PLL_CTRL
- 7.6.1.40 PIN_FUNCTION
- 7.6.1.41 GPIO_CONFIG
- 7.6.1.42 GPIO_IN
- 7.6.1.43 GPIO_OUT
- 7.6.1
Register Descriptions
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機械數(shù)據(jù) (封裝 | 引腳)
- RNF|26
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
5 Pin Configuration and Functions
RNF Package
26-Pin VQFN With Thermal Pad
Top View
Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NUMBER | NAME | ||
| 1 | FB_B2 | A | Output voltage feedback (positive) for Buck2. |
| 2 | EN3 | D/I/O | Programmable enable signal for buck regulators (can be also configured to select between two buck output voltage levels). Alternative function is GPIO3. |
| 3 | CLKIN | D/I | External clock input. Connect to ground if external clock is not used. |
| 4, 17, Thermal Pad | AGND | G | Ground |
| 5 | SCL | D/I | Serial interface clock input for I2C access. Connect a pullup resistor. |
| 6 | SDA | D/I/O | Serial interface data input and output for I2C access. Connect a pullup resistor. |
| 7 | EN1 | D/I/O | Programmable Enable signal for buck regulators (can be also configured to select between two buck output voltage levels). Alternative function is GPIO1. |
| 8 | FB_B0 | A | Output voltage feedback (positive) for Buck0 |
| 9 | VIN_B0 | P | Input for Buck0. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed. |
| 10 | SW_B0 | A | Buck0 switch node |
| 11 | PGND_B01 | G | Power ground for Buck0 and Buck1 |
| 12 | SW_B1 | A | Buck1 switch node |
| 13 | VIN_B1 | P | Input for Buck1. The separate power pins VIN_Bx are not connected together internally – VIN_Bx pins must be connected together in the application and be locally bypassed. |
| 14 | FB_B1 | A | Output voltage feedback (positive) for Buck1. |
| 15 | EN2 | D/I/O | Programmable enable signal for Buck regulators (can be also configured to select between two buck output voltage levels). Alternative function is GPIO2. |
| 16 | PGOOD | D/O | Power Good indication signal |
| 18 | VANA | P | Supply voltage for analog and digital blocks. Must be connected to same node as with VIN_Bx. |
| 19 | nINT | D/O | Open-drain interrupt output, active LOW |
| 20 | NRST | D/I | Reset signal for the device. |
| 21 | FB_B3 | A | Output voltage feedback (positive) for Buck3. |
| 22 | VIN_B3 | P | Input for Buck3. The separate power pins VIN_Bx are not connected together internally – VIN_Bx pins must be connected together in the application and be locally bypassed. |
| 23 | SW_B3 | A | Buck3 switch node |
| 24 | PGND_B23 | G | Power Ground for Buck2 and Buck3 |
| 25 | SW_B2 | A | Buck2 switch node |
| 26 | VIN_B2 | P | Input for Buck2. The separate power pins VIN_Bx are not connected together internally – VIN_Bx pins must be connected together in the application and be locally bypassed. |
| A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin | |||