ZHCSH29B April 2017 – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Descriptions
- 7.3.1 DC-DC Converters
- 7.3.2 Sync Clock Functionality
- 7.3.3 Power-Up
- 7.3.4 Regulator Control
- 7.3.5 Enable and Disable Sequences
- 7.3.6 Device Reset Scenarios
- 7.3.7 Diagnosis and Protection Features
- 7.3.8 GPIO Signal Operation
- 7.3.9 Digital Signal Filtering
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1
Register Descriptions
- 7.6.1.1 OTP_REV
- 7.6.1.2 BUCK0_CTRL1
- 7.6.1.3 BUCK1_CTRL1
- 7.6.1.4 BUCK2_CTRL1
- 7.6.1.5 BUCK3_CTRL1
- 7.6.1.6 BUCK0_VOUT
- 7.6.1.7 BUCK0_FLOOR_VOUT
- 7.6.1.8 BUCK1_VOUT
- 7.6.1.9 BUCK1_FLOOR_VOUT
- 7.6.1.10 BUCK2_VOUT
- 7.6.1.11 BUCK2_FLOOR_VOUT
- 7.6.1.12 BUCK3_VOUT
- 7.6.1.13 BUCK3_FLOOR_VOUT
- 7.6.1.14 BUCK0_DELAY
- 7.6.1.15 BUCK1_DELAY
- 7.6.1.16 BUCK2_DELAY
- 7.6.1.17 BUCK3_DELAY
- 7.6.1.18 GPIO2_DELAY
- 7.6.1.19 GPIO3_DELAY
- 7.6.1.20 RESET
- 7.6.1.21 CONFIG
- 7.6.1.22 INT_TOP1
- 7.6.1.23 INT_TOP2
- 7.6.1.24 INT_BUCK_0_1
- 7.6.1.25 INT_BUCK_2_3
- 7.6.1.26 TOP_STAT
- 7.6.1.27 BUCK_0_1_STAT
- 7.6.1.28 BUCK_2_3_STAT
- 7.6.1.29 TOP_MASK1
- 7.6.1.30 TOP_MASK2
- 7.6.1.31 BUCK_0_1_MASK
- 7.6.1.32 BUCK_2_3_MASK
- 7.6.1.33 SEL_I_LOAD
- 7.6.1.34 I_LOAD_2
- 7.6.1.35 I_LOAD_1
- 7.6.1.36 PGOOD_CTRL1
- 7.6.1.37 PGOOD_CTRL2
- 7.6.1.38 PGOOD_FLT
- 7.6.1.39 PLL_CTRL
- 7.6.1.40 PIN_FUNCTION
- 7.6.1.41 GPIO_CONFIG
- 7.6.1.42 GPIO_IN
- 7.6.1.43 GPIO_OUT
- 7.6.1
Register Descriptions
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.3.5 Enable and Disable Sequences
The LP87524B/J/P-Q1 device supports start-up and shutdown sequencing with programmable delays for different regulator outputs using single EN1/2/3 control signal. The regulator is selected for delayed control with:
- EN_BUCKx = 1 (in BUCKx_CTRL1 register)
- EN_PIN_CTRLx = 1 (in BUCKx_CTRL1 register)
- EN_ROOF_FLOORx = 0 (in BUCKx_CTRL1 register)
- BUCKx_VSET[7:0] = Required voltage when ENx is high (in BUCKx_VOUT register)
- The ENABLE pin for control is selected with BUCKx_EN_PIN_SELECT[1:0] (in BUCKx_CTRL1 register)
- The delay from rising edge of ENx signal to the regulator enable is set by BUCKx_STARTUP_DELAY[3:0] bits (in BUCKx_DELAY register) and
- The delay from falling edge of ENx signal to the regulator disable is set by BUCKx_SHUTDOWN_DELAY[3:0] bits (in BUCKx_DELAY register)
There are four time steps available for start-up and shutdown sequences. The delay times are selected with DOUBLE_DELAY bit in CONFIG register and HALF_DELAY bit in PGOOD_CTRL2 register as shown in Table 4.
Table 4. Start-up and Shutdown Delays
| X_STARTUP_DELAY /
X_SHUTDOWN_DELAY |
DOUBLE_DELAY = 0
HALF_DELAY = 1 |
DOUBLE_DELAY = 1
HALF_DELAY = 1 |
DOUBLE_DELAY = 0
HALF_DELAY = 0 |
DOUBLE_DELAY = 1
HALF_DELAY = 0 |
|---|---|---|---|---|
| 0000 | 0 ms | 0 ms | 0 ms | 0 ms |
| 0001 | 0.32 ms | 0.64 ms | 1 ms | 2 ms |
| 0010 | 0.64 ms | 1.28 ms | 2 ms | 4 ms |
| 0011 | 0.96 ms | 1.92 ms | 3 ms | 6 ms |
| 0100 | 1.28 ms | 2.56 ms | 4 ms | 8 ms |
| 0101 | 1.6 ms | 3.2 ms | 5 ms | 10 ms |
| 0110 | 1.92 ms | 3.84 ms | 6 ms | 12 ms |
| 0111 | 2.24 ms | 4.48 ms | 7 ms | 14 ms |
| 1000 | 2.56 ms | 5.12 ms | 8 ms | 16 ms |
| 1001 | 2.88 ms | 5.76 ms | 9 ms | 18 ms |
| 1010 | 3.2 ms | 6.4 ms | 10 ms | 20 ms |
| 1011 | 3.52 ms | 7.04 ms | 11 ms | 22 ms |
| 1100 | 3.84 ms | 7.68 ms | 12 ms | 24 ms |
| 1101 | 4.16 ms | 8.32 ms | 13 ms | 26 ms |
| 1110 | 4.48 ms | 8.96 ms | 14 ms | 28 ms |
| 1111 | 4.8 ms | 9.6 ms | 15 ms | 30 ms |
An example of start-up and shutdown sequences is shown in Figure 10 and Figure 11. The start-up and shutdown delays for the Buck0/1 regulators are 1 ms and 4 ms and for the Buck2/3 regulators 3 ms and 1 ms. The delay settings are used only for enable/disable control with EN1/2/3 signals, not for Roof/Floor control.
Figure 10. Typical Start-Up and Shutdown Sequencing 
Figure 11. Start-Up and Shutdown Sequencing With Short ENx Low and High Periods