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ZHCSH29B April 2017 – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1

PRODUCTION DATA.

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機械數(shù)據(jù) (封裝 | 引腳)

RNF|26

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ T_J ≤ +140°C, C_POL = 22 µF / phase, specified V_VANA, V_{VIN_Bx} , V_NRST, V_{VOUT_Bx} and I_OUT range, unless otherwise noted. Typical values are at T_J = 25°C, V_VANA = V_{VIN_Bx} = 3.7 V, and V_OUT = 1 V, unless otherwise noted.⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
EXTERNAL COMPONENTS
C_IN	Input filtering capacitance	Connected from VIN_Bx to PGND_Bx	1.9	10		µF
C_OUT	Output filtering Capacitance, local	Capacitance per phase	10	22		µF
C_POL	Point-of-Load (POL) capacitance	Optional POL capacitance per phase		22		µF
C_OUT-TOTAL	Output capacitance, total (local and POL)	Total output capacitance, 1-phase output			100	µF
ESR_C	Input and output capacitor ESR	[1-10] MHz		2	10	mΩ
L	Inductor	Inductance of the inductor		0.47		µH
L	Inductor	Inductance of the inductor	–30%		30%
DCR_L	Inductor DCR			25		mΩ
BUCK REGULATOR
V_{VIN_Bx}	Input voltage range		2.8	3.7	5.5	V
V_{VOUT_Bx}	Output voltage	Programmable voltage range, 2.8 V ≤ V_{VIN_Bx} ≤ 4 V	0.6		3.36	V
		Programmable voltage range, 2.8 V ≤ V_{VIN_Bx} ≤ 5.5 V	1.0		3.36	V
		Step size, 0.6 V ≤ V_OUT < 0.73 V		10		mV
		Step size, 0.73 V ≤ V_OUT < 1.4 V		5
		Step size, 1.4 V ≤ V_OUT ≤ 3.36 V		20
I_OUT	Output current, LP87524B/J	Buck0, Buck1			1.5⁽³⁾	A
		Buck2: V_IN ≥ 3 V			4⁽³⁾
		Buck2: 2.8 V ≤ V_IN < 3 V			3⁽³⁾
		Buck3			2.5⁽³⁾
I_OUT	Output current, LP87524P	Buck0, Buck2			3⁽³⁾	A
		Buck1			1.5⁽³⁾
		Buck3			2.5⁽³⁾
	Input and output voltage difference	Minimum voltage between VIN_x and V_OUT to fulfill the electrical characteristics	0.5			V
V_{VOUT_DC}	DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature	V_OUT < 1 V, PWM mode	–20		20	mV
		V_OUT ≥ 1 V, PWM mode	–2%		2%
		V_OUT < 1 V, PFM mode	–20		40	mV
		V_OUT ≥ 1 V, PFM mode	–2%		2% + 20 mV
	Ripple voltage	PWM mode, ESR_C < 2 mΩ, L = 0.47 µH		4		mV_p-p
	Ripple voltage	PFM mode, L = 0.47 µH		14		mV_p-p
DC_LNR	DC line regulation	I_OUT = I_OUT(max)		0.1		%/V
DC_LDR	DC load regulation in PWM mode	V_OUT = 1 V, I_OUT from 0 to I_OUT(max)		0.8%
T_LDSR	Transient load step response	I_OUT = 0 A to 2 A, T_R = T_F = 10 µs, PWM mode, C_OUT = 22 µF, L = 0.47 µH, C_POL = 22 µF	–3%		3%	mV
T_LDSR	Transient load step response	I_OUT = 0.1 A to 2 A, T_R = T_F = 1 µs, PWM mode, C_OUT = 22 µF, L = 0.47 µH, C_POL = 22 µF		±40		mV
T_LNSR	Transient line response	V_{VIN_Bx} stepping 3 V ↔ 3.5 V, T_R = T_F = 10 µs, I_OUT = I_OUT(max)		±5		mV
I_{LIM FWD}	Forward current limit (peak for every switching cycle), LP87524B/J	Buck0, Buck1: V_{VIN_Bx} ≥ 3 V	2.3	2.7	3.0	A
		Buck0, Buck1: 2.8 V ≤ V_{VIN_Bx} < 3 V	2.0	2.7	3.0
		Buck2: V_{VIN_Bx} ≥ 3 V	4.7	5.4	6.0
		Buck2: 2.8 V ≤ V_{VIN_Bx} < 3 V	4.0	5.4	6.0
		Buck3: V_{VIN_Bx} ≥ 3 V	4.2	4.8	5.4
		Buck3: 2.8 V ≤ V_{VIN_Bx} < 3 V	3.6	4.8	5.4
I_{LIM FWD}	Forward current limit (peak for every switching cycle), LP87524P	Buck0, Buck2: V_{VIN_Bx} ≥ 3 V	3.8	4.3	4.8	A
		Buck0, Buck2: 2.8 V ≤ V_{VIN_Bx} < 3 V	3.2	4.3	4.8
		Buck1: V_{VIN_Bx} ≥ 3 V	2.3	2.7	3.0
		Buck1: 2.8 V ≤ V_{VIN_Bx} < 3 V	2.0	2.7	3.0
		Buck3: V_{VIN_Bx} ≥ 3 V	4.2	4.8	5.4
		Buck3: 2.8 V ≤ V_{VIN_Bx} < 3 V	3.6	4.8	5.4
I_{LIM NEG}	Negative current limit / phase (peak for every switching cycle)		1.6	2	2.4	A
R_{DS(ON) HS FET}	On-resistance, high-side FET	Each phase, between VIN_Bx and SW_Bx pins (I = 1 A)		29	65	mΩ
R_{DS(ON) LS FET}	On-resistance, low-side FET	Each phase, between SW_Bx and PGND_Bx pins (I = 1 A)		17	35	mΩ
f_SW	Switching frequency, PWM mode	V_OUT > 0.8	3.6	4	4.4	MHz
		0.6 < V_OUT ≤ 0.8	2.7	3	3.3
		V_OUT = 0.6	1.8	2	2.2
	Start-up time (soft start)	From ENx to V_OUT = 0.35 V (slew-rate control begins), C_{OUT_TOTAL} = 44 µF / phase		200		µs
	Output voltage slew-rate⁽⁴⁾		3.23	3.8	4.4	mV/µs
I_PFM-PWM	PFM-to-PWM - current threshold⁽⁵⁾			600		mA
I_PWM-PFM	PWM-to-PFM - current threshold⁽⁵⁾			200		mA
	Output pulldown resistance	Regulator disabled	160	230	300	Ω
	Output voltage monitoring for PGOOD pin	Overvoltage monitoring (compared to DC output voltage level, V_{VOUT_DC})	39	50	64	mV
		Undervoltage monitoring (compared to DC output voltage level, V_{VOUT_DC})	–53	–40	–29	mV
		Debounce time during regulator enable PGOOD_SET_DELAY = 0	4		10	µs
		Debounce time during regulator enable PGOOD_SET_DELAY = 1	10	11	13	ms
		Deglitch time during operation and after voltage change	4		10	µs
	Powergood threshold for interrupt BUCKx_PG_INT, difference from final voltage	Rising ramp voltage, enable or voltage change	–20	–14	–8	mV
		Falling ramp voltage, voltage change	8	14	20	mV
	Powergood threshold for status bit BUCKx_PG_STAT	During operation, status signal is forced to '0' during voltage change	–20	–14	–8	mV
EXTERNAL CLOCK AND PLL
	External input clock	Nominal frequency	1		24	MHz
		Nominal frequency step size		1		MHz
		Required accuracy from nominal frequency	–30%		10%
	External clock detection	Delay for missing clock detection			1.8	µs
	External clock detection	Delay and debounce for clock detection			20	µs
	Clock change delay (internal to external)	Delay from valid clock detection to use of external clock		600		µs
	PLL output clock jitter	Cycle to cycle		300		ps, p-p
PROTECTION FUNCTIONS
	Thermal warning	Temperature rising, TDIE_WARN_LEVEL = 0	115	125	135	°C
		Temperature rising, TDIE_WARN_LEVEL = 1	127	137	147
		Hysteresis		20
	Thermal shutdown	Temperature rising	140	150	160	°C
	Thermal shutdown	Hysteresis		20		°C
VANA_OVP	VANA overvoltage	Voltage rising	5.6	5.8	6.1	V
		Voltage falling	5.45	5.73	5.96	V
		Hysteresis	40			mV
VANA_UVLO	VANA undervoltage lockout	Voltage rising	2.51	2.63	2.75	V
VANA_UVLO	VANA undervoltage lockout	Voltage falling	2.5	2.6	2.7	V
LOAD CURRENT MEASUREMENT
	Current measurement range	Output current for maximum code			20.47	A
	Resolution	LSB		20		mA
	Measurement accuracy	I_OUT > 1 A		<10%
	Measurement time	PFM mode (automatically changing to PWM mode for the measurement)		45		µs
	Measurement time	PWM mode		4		µs
CURRENT CONSUMPTION
	Shutdown current consumption	From VANA and VIN_Bx pins: NRST = 0 V, VANA = VIN_Bx = 3.7 V		1.4		µA
	Standby current consumption, regulators disabled	From VANA and VIN_Bx pins: NRST = 1.8 V, VANA = VIN_Bx = 3.7 V		6.7		µA
	Active current consumption in PFM mode, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled	From VANA and VIN_Bx pins: NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, I_OUT = 0 mA, not switching		57		µA
	Active current consumption during PWM operation, per phase			19		mA
	PLL and clock detector current consumption	Additional current consumption when internal RC oscillator, clock detector and PLL are enabled		2		mA
DIGITAL INPUT SIGNALS NRST, EN1, EN2, EN3, EN4, SCL, SDA, GPIO1, GPIO2, GPIO3, CLKIN
V_IL	Input low level				0.4	V
V_IH	Input high level		1.2			V
V_HYS	Hysteresis of Schmitt Trigger inputs		10	77	200	mV
	ENx pulldown resistance	ENx_PD = 1		500		kΩ
	NRST pulldown resistance	Always present	650	1150	1700	kΩ
DIGITAL OUTPUT SIGNALS nINT
V_OL	Output low level	I_SOURCE = 2 mA			0.4	V
R_P	External pullup resistor	To VIO supply		10		kΩ
DIGITAL OUTPUT SIGNALS SDA
V_OL	Output low level	I_SOURCE = 10 mA			0.4	V
DIGITAL OUTPUT SIGNALS PGOOD, GPIO1, GPIO2, GPIO3
V_OL	Output low level	I_SOURCE = 2 mA			0.4	V
V_OH	Output high level, configured to push-pull	I_SINK = 2 mA	V_VANA – 0.4		V_VANA	V
V_PU	Supply voltage for external pull-up resistor, configured to open-drain				V_VANA	V
R_PU	External pullup resistor, configured to open-drain			10		kΩ
ALL DIGITAL INPUTS
I_LEAK	Input current	All logic inputs over pin voltage range (except NRST)	−1		1	µA

(1) All voltage values are with respect to network ground.

(2) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm.

(3) The maximum output current can be limited by the forward current limit I_{LIM FWD} and by the junction temperature. The power dissipation inside the die depends on the length of the current pulse and efficiency and the junction temperature may increase to thermal shutdown level if the board and ambient temperatures are high.

(4) Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates.

(5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and the inductor current level.