Each channel of the LM5170-Q1 has a robust 5-A (peak) half bridge driver to drive external N-channel power MOSFETs. As shown in Figure 8-8, the low-side drive is directly powered by VCC, and the high-side driver by the bootstrap capacitor C_BT. During the on-time of the low-side driver, the SW pin is pulled down to PGND and C_BT is charged by VCC through the boot diode D_BT. TI recommends selecting a 0.1-μF or larger ceramic capacitor for C_BT, and an ultra-fast diode of 1 A and 100-V ratings for D_BT. TI also strongly recommends users to add a 2-Ω to 5-Ω resistor (R_BT) in series with D_BT to limit the surge charging current and improve the noise immunity of the high-side driver.

Figure 8-8 Bootstrap Circuit for High-Side Bias Supply

During start-up in buck mode, C_BT may not be charged initially; the LM5170-Q1 then holds off the high-side driver outputs (HO1 and HO2) and sends LO pulses of 200-ns width in consecutive cycles to pre-charge C_BT. When the boot voltage is greater than the 6.5-V boot UV threshold, the high-side drivers output PWM signals at the HO1 and HO2 pins for normal switching action.

During start-up in boost mode, C_BT is naturally charged by the normal turnon of the low side MOSFET, therefore there is no such 200-ns pre-charge pulse at the LO pins.

To prevent shoot-through between the high-side and low-side power MOSFETs on the same half bridge leg, two types of dead time schemes can be chosen with the DT pin: the programmable dead time or built-in adaptive dead time.

To program the dead time, place a resistor R_DT across the DT and AGND pins as shown in Figure 8-9.

The dead time t_DT as depicted in Figure 8-10 is determined by Equation 15:

Equation 15.

Note that this equation is valid for programming t_DT between 20 ns and 250 ns. When the power MOSFET is connected to the gate drive, its gate input capacitance C_ISS becomes a load of the gate drive output, and the HO and LO slew rate are reduced, leading to a reduced effective t_DT between the high- and low-side MOSFETs. The user should evaluate the effective t_DT to make sure it is adequate to prevent shoot-through between the high- and low-side MOSFETs.

When the DT programmability is not used, simply connect the DT pin to VCC as shown in Figure 8-11, to activate the built-in adaptive dead time. The adaptive dead time is implemented by real time monitoring of a driver’s output (either HO or LO) by the other driver (LO or HO) of the same half bridge switch leg, as shown in Figure 8-11 and Figure 8-12. Only when a driver’s output voltage falls below 1.25 V does the other driver starts turnon. The effectiveness of adaptive dead time is greatly reduced if a series gate resistor is used, or if the PCB traces of the gate drive have excessive impedance due to poor layout design.

Figure 8-9 Dead Time Programming With DT Pin (Only One Channel is Shown)

Figure 8-10 Gate Drive Dead Time (Only One Channel is Shown)

Figure 8-11 Dead Time Programming With DT Pin (Only One Channel is Shown)

Figure 8-12 Adaptive Dead Time (Only One Channel is Shown)