SNVSCU3 October 2025 LM5137
PRODMIX
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Related Products
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Input Voltage Range (VIN)
- 7.3.2 Bias Supply Regulator (VCC, BIAS1/VOUT1, VDDA)
- 7.3.3 Precision Enable (EN1, EN2)
- 7.3.4 Switching Frequency (RT)
- 7.3.5 Pulse Frequency Modulation and Synchronization (PFM/SYNC)
- 7.3.6 Synchronization Out (SYNCOUT)
- 7.3.7 Dual Random Spread Spectrum (DRSS)
- 7.3.8 Configurable Soft Start (RSS)
- 7.3.9 Output Voltage Setpoints (FB1, FB2)
- 7.3.10 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)
- 7.3.11 Inductor Current Sense (ISNS1+, BIAS1/VOUT1, ISNS2+, VOUT2)
- 7.3.12 Minimum Controllable On-Time
- 7.3.13 100% Duty Cycle Capability
- 7.3.14 MOSFET Gate Drivers (HO1, HO2, LO1, LO2)
- 7.3.15 Output Configurations (CNFG)
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
Design 1 – Dual 5V and 3.3V, 20A Buck Regulator for 12V
Input Applications
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 Custom Design With WEBENCH? Tools
- 8.2.1.2.2 Custom Design With Excel Quickstart Tool
- 8.2.1.2.3 Inductor Calculations
- 8.2.1.2.4 Shunt Resistors
- 8.2.1.2.5 Ceramic Output Capacitors
- 8.2.1.2.6 Ceramic Input Capacitors
- 8.2.1.2.7 Feedback Resistors
- 8.2.1.2.8 Input Voltage UVLO Resistors
- 8.2.1.2.9 Compensation Components
- 8.2.1.3 Application Curves
- 8.2.2 Design 2 – Two-Phase, Single-Output Synchronous Buck Regulator
- 8.2.3 Design 3 – 12V, 20A, 400kHz, Two-Phase Buck Regulator for 48V Server Applications
- 8.2.1
Design 1 – Dual 5V and 3.3V, 20A Buck Regulator for 12V
Input Applications
- 8.3 Power Supply Recommendations
- 8.4 Layout
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
7.3.15.2 Single-Output Interleaved Operation
Based on a resistor RCNFG connected from CNFG to AGND, configure the LM5137 as for single-output interleaved operation. As shown in Table 7-4, use 41.2kΩ to disable DRSS and 54.9kΩ or 71.5kΩ to enable DRSS at 5% or 10% frequency spreading, respectively. This setup disables the error amplifier of channel 2 and places the error amplifier in a high impedance state. The controller is then in a primary, secondary configuration, and the SYNCOUT clock is 180° lagging HO2 (or 180° leading HO1).
As shown in Figure 7-8, connect COMP1 to COMP2 and use FB1 to set the output voltage setpoint. Use PG1 as needed and leave PG2 open or tied to GND.
| RCNFG | PRIMARY / SECONDARY | DRSS | INDEPENDENT OR INTERLEAVED OUTPUTS |
|---|---|---|---|
| 41.2kΩ | Primary | OFF | Interleaved |
| 54.9kΩ | Primary | DRSS1 | Interleaved |
| 71.5kΩ | Primary | DRSS2 | Interleaved |
Figure 7-8
LM5137 Two-phase Regulator Schematic Configured
for Single-output Interleaved Operation