5 Pin Configuration and Functions

Connect the exposed pad on the bottom to AGND and PGND on the PCB.

Figure 5-1 RHA Package, 36-Pin VQFN With Wettable Flanks (Top View)

Table 5-1 Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
FB2	1	I	Connect FB2 through a 7.5kΩ, 24.9kΩ or 48.7kΩ resistor to VDDA to set the output voltage at 3.3V, 5V or 12V, respectively. Alternatively, use a resistive divider from VOUT2 to FB2 to set the output voltage setpoint of channel 2 between 0.8V and 60V. The FB2 regulation voltage is 0.8V.
VOUT2	3	I	Output voltage sense and the current sense amplifier input of channel 2. Connect VOUT2 to the output side of the channel 2 current sense resistor (or to the relative sense capacitor terminal if inductor DCR current sensing is used).
ISNS2+	4	I	Channel 2 current sense amplifier input. Connect ISNS2+ to the inductor side of the external current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a low-current Kelvin connection.
PG2	5	O	An open-drain output that goes low if VOUT2 is outside a specific regulation window
EN2	6	I	An active high input (V_EN2 > 1V typical) enables channel 2. If V_EN2 < 0.5V, channel 2 is disabled and is in shutdown mode unless a SYNC signal is present at PFM/SYNC. EN2 must never be left floating.
VIN	8	P	Supply voltage input source for the VCC regulator
HO2	9	P	Channel 2 high-side gate driver output
SW2	10	P	Switching node of the channel 2 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET.
CBOOT2	11	P	Channel 2 high-side driver supply for bootstrap gate drive
LO2	12	P	Channel 2 low-side gate driver output
PGND	13	G	Power ground connection pin for the low-side MOSFET gate driver
VCC	14	P	VCC bias supply pin. Connect a ceramic capacitor between VCC and PGND.
LO1	15	P	Channel 1 low-side gate driver output
CBOOT1	16	P	Channel 1 high-side driver supply for bootstrap gate drive
SW1	17	P	Switching node of the channel 1 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET.
HO1	18	P	Channel 1 high-side gate driver output
EN1	20	I	An active high input (V_EN1 > 1V typical) enables channel 1. If V_EN1 < 0.5V, channel 1 is disabled and is in shutdown mode unless a SYNC signal is present at PFC/SYNC. EN1 must never be left floating.
PG1	21	O	An open-collector output that goes low if VOUT1 is outside a specified regulation window.
ISNS1+	22	I	Channel 1 current sense amplifier input. Connect ISNS1+ to the inductor side of the external current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a low-current Kelvin connection.
BIAS1/VOUT1	23	I	If V_BIAS1 > 4.3V, BIAS1 becomes the supply voltage to the internal VCC regulator. BIAS1 also acts as the primary VOUT1 sensing and the current sense amplifier input for channel 1. Connect BIAS/VOUT1 to the output side of the channel 1 current sense resistor.
CNFG	26	I	Connect a resistor from CNFG to GND to set the output configuration and to activate DRSS at one of two modulation frequencies (or to disable). See also Table 7-1.
FB1	25	I	Connect FB1 through a 7.5kΩ, 24.9kΩ or 48.7kΩ resistor to VDDA to set the output voltage at 3.3V, 5V or 12V, respectively. Alternatively, use a resistive divider from VOUT1 to FB1 to set the output voltage setpoint of channel 1 between 0.8V and 60V. The FB1 regulation voltage is 0.8V.
COMP1	28	O	Output of the channel 1 transconductance error amplifier. COMP1 is high impedance in interleaved or secondary mode. Pulling COMP1 below 100mV in interleaved mode disables the HO1 and LO1 gate driver outputs.
RSS	29	I	Connect a resistor from RSS to GND to set the soft-start time between 1.5ms and 20ms
RT	30	O	Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100kHz and 2.2MHz.
AGND	31	G	Analog ground connection. Ground return for the internal voltage reference and analog circuits.
VDDA	32	P	Internal analog bias regulator output. Connect a 1μF ceramic decoupling capacitor from VDDA to AGND.
SYNCOUT	33	O	SYNCOUT is a logic-level signal with a rising edge approximately 90° lagging HO1 (or 90° leading HO2). When SYNCOUT is used to synchronize a second LM5137 controller, the phases operate at 0°, 90°, 180° and 270° as needed.
PFM/SYNC	34	I	Connect PFM/SYNC to VDDA to operate the LM5137 in PFM mode. Connect PFM/SYNC to GND to enable forced PWM (FPWM) mode with continuous conduction at light loads. Use PFM/SYNC as a synchronization input to synchronize the internal oscillator to an external clock.
COMP2	35	O	Output of the channel 2 transconductance error amplifier. COMP2 is high impedance in single-output interleaved mode. Pulling COMP2 below 100mV in interleaved mode disables the HO2 and LO2 gate driver outputs.
GND	2, 7, 19, 24, 27, 36	G	Unused pins – connect to the exposed pad on the PCB.

(1) P = Power, G = Ground, I = Input, O = Output