SNVSCU3 October 2025 LM5137
PRODMIX
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Related Products
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Input Voltage Range (VIN)
- 7.3.2 Bias Supply Regulator (VCC, BIAS1/VOUT1, VDDA)
- 7.3.3 Precision Enable (EN1, EN2)
- 7.3.4 Switching Frequency (RT)
- 7.3.5 Pulse Frequency Modulation and Synchronization (PFM/SYNC)
- 7.3.6 Synchronization Out (SYNCOUT)
- 7.3.7 Dual Random Spread Spectrum (DRSS)
- 7.3.8 Configurable Soft Start (RSS)
- 7.3.9 Output Voltage Setpoints (FB1, FB2)
- 7.3.10 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)
- 7.3.11 Inductor Current Sense (ISNS1+, BIAS1/VOUT1, ISNS2+, VOUT2)
- 7.3.12 Minimum Controllable On-Time
- 7.3.13 100% Duty Cycle Capability
- 7.3.14 MOSFET Gate Drivers (HO1, HO2, LO1, LO2)
- 7.3.15 Output Configurations (CNFG)
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
Design 1 – Dual 5V and 3.3V, 20A Buck Regulator for 12V
Input Applications
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 Custom Design With WEBENCH? Tools
- 8.2.1.2.2 Custom Design With Excel Quickstart Tool
- 8.2.1.2.3 Inductor Calculations
- 8.2.1.2.4 Shunt Resistors
- 8.2.1.2.5 Ceramic Output Capacitors
- 8.2.1.2.6 Ceramic Input Capacitors
- 8.2.1.2.7 Feedback Resistors
- 8.2.1.2.8 Input Voltage UVLO Resistors
- 8.2.1.2.9 Compensation Components
- 8.2.1.3 Application Curves
- 8.2.2 Design 2 – Two-Phase, Single-Output Synchronous Buck Regulator
- 8.2.3 Design 3 – 12V, 20A, 400kHz, Two-Phase Buck Regulator for 48V Server Applications
- 8.2.1
Design 1 – Dual 5V and 3.3V, 20A Buck Regulator for 12V
Input Applications
- 8.3 Power Supply Recommendations
- 8.4 Layout
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RHA|36
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RHA|36
訂購信息
8.2.1.2.4 Shunt Resistors
- Calculate the shunt resistance based on a maximum
peak current capability at least 20% higher than the peak inductor current at
full load to provide sufficient margin during start-up and load-step transients.
Use Equation 32 to calculate the shunt resistances. Equation 32.
where
- VCS(th) is the 60mV current limit threshold.
- Select a standard resistance value of 2m? for both shunts. A 1225 footprint component with wide aspect ratio termination design provides a 3W power rating, parasitic inductance (ESL) less than 1nH, and compact PCB layout. Carefully adhere to the layout guidelines in Layout Guidelines to make sure that noise and DC errors do not corrupt the current-sense voltages measured differentially at the [ISNS1+, VOUT1] and [ISNS2+, VOUT2] pins.
- Place the shunt resistor close to the inductor.
- Use Kelvin sense connections and route the sense lines differentially from the shunt to the applicable pins of the LM5137.
- The current-sense-to-output propagation delay
(related to the current limit comparator, internal logic and power MOSFET gate
drivers) causes the peak current to increase above the calculated current limit
threshold. For a total propagation delay of tCS-DELAY of 70ns, use
Equation 33 to calculate the worst-case peak inductor current with the
output shorted. Equation 33.
- Based on this result, select an inductor for each channel with saturation current greater than 33A across the full operating temperature range.