SNVSCU3 October 2025 LM5137
PRODMIX
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Related Products
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Input Voltage Range (VIN)
- 7.3.2 Bias Supply Regulator (VCC, BIAS1/VOUT1, VDDA)
- 7.3.3 Precision Enable (EN1, EN2)
- 7.3.4 Switching Frequency (RT)
- 7.3.5 Pulse Frequency Modulation and Synchronization (PFM/SYNC)
- 7.3.6 Synchronization Out (SYNCOUT)
- 7.3.7 Dual Random Spread Spectrum (DRSS)
- 7.3.8 Configurable Soft Start (RSS)
- 7.3.9 Output Voltage Setpoints (FB1, FB2)
- 7.3.10 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)
- 7.3.11 Inductor Current Sense (ISNS1+, BIAS1/VOUT1, ISNS2+, VOUT2)
- 7.3.12 Minimum Controllable On-Time
- 7.3.13 100% Duty Cycle Capability
- 7.3.14 MOSFET Gate Drivers (HO1, HO2, LO1, LO2)
- 7.3.15 Output Configurations (CNFG)
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
Design 1 – Dual 5V and 3.3V, 20A Buck Regulator for 12V
Input Applications
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 Custom Design With WEBENCH? Tools
- 8.2.1.2.2 Custom Design With Excel Quickstart Tool
- 8.2.1.2.3 Inductor Calculations
- 8.2.1.2.4 Shunt Resistors
- 8.2.1.2.5 Ceramic Output Capacitors
- 8.2.1.2.6 Ceramic Input Capacitors
- 8.2.1.2.7 Feedback Resistors
- 8.2.1.2.8 Input Voltage UVLO Resistors
- 8.2.1.2.9 Compensation Components
- 8.2.1.3 Application Curves
- 8.2.2 Design 2 – Two-Phase, Single-Output Synchronous Buck Regulator
- 8.2.3 Design 3 – 12V, 20A, 400kHz, Two-Phase Buck Regulator for 48V Server Applications
- 8.2.1
Design 1 – Dual 5V and 3.3V, 20A Buck Regulator for 12V
Input Applications
- 8.3 Power Supply Recommendations
- 8.4 Layout
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
8.2.1.2.5 Ceramic Output Capacitors
- Use Equation 34 to estimate the output capacitance required to manage the output voltage
overshoot during a load-off transient of 10A, assuming a load transient deviation
specification of 100mV. Equation 34.
- Noting the voltage coefficient of ceramic capacitors where the effective capacitance decreases significantly with applied voltage, select four 47μF, 10V, X7R, 1210 ceramic output capacitors for each channel. According to the design tool from the capacitor vendor, these capacitors are each effectively 32μF and 41μF at 5V and 3.3V DC voltage, respectively.
- Use Equation 35 to estimate the peak-to-peak output voltage ripple of channel 1 at
nominal input voltage. Equation 35.
where
- RESR is the effective equivalent series resistance (ESR) of the output capacitors.
- 128μF is the total effective (derated) ceramic output capacitance at 5V.
- Use Equation 36 to calculate the output capacitor RMS ripple current at maximum input
voltage. Verify that the output capacitor RMS ripple current at maximum input voltage is
within the capacitor ripple current rating. Equation 36.
