ZHCSHX0C March 2018 – January 2023 DS90UB936-Q1
PRODUCTION DATA
The DS90UB936-Q1 can support single or dual simultaneous inputs to Rx port 0 and Rx port 1. The Receiver port control register RX_PORT_CTL 0x0C (Table 7-31) allows for disabling one or both of the Rx inputs when not in use. These bits can only be written by a local I2C controller at the deserializer side of the FPD-Link.
Each FPD-Link III Receive port has a unique set of registers that provides control and status corresponding to Rx port 0 or Rx port 1. Control of the FPD-Link III port registers is assigned by the FPD3_PORT_SEL register, which sets the page controls for reading or writing individual ports unique registers. For each of the FPD-Link III Receive Ports, the FPD3_PORT_SEL 0x4C register defaults to selecting that port’s registers as detailed in register description (Table 7-86).
As an alternative to paging to access FPD-Link III Receive unique port registers, separate I2C addresses may be enabled to allow direct access to the port-specific registers. The Port I2C address registers allow programming a separate 7-bit I2C address to allow access to unique, port-specific registers without paging. I2C commands to these assigned I2C addresses are also allowed access to all shared registers (see Table 7-179).