4 Revision History
Changes from Revision B (June 2018) to Revision C (January 2023)
- 更新了整個文檔中的表格、圖和交叉參考的編號格式Go
- 將所有舊術語實例更改為控制器和目標Go
- 更新了兼容器件列表以包含 DS90UB953-Q1Go
- Revised the PDB pin voltage for normal operationGo
- Changed the VDD11 pin descriptions for clarityGo
- Added a link to Design Requirements under the RIN pinsGo
- Updated the VIH and VIL specifications of pins PDB,
XIN/REFCLK, and VDD_SELGo
- Removed the mention of CSI-2 non-synchronous clocking
modeGo
- Changed the bits that need to be modified for Clock Mode Go
- Removed the mention of setting the REF_CLK_MODE bit as it is a
reserved bitGo
- Fixed typos in the internal FrameSync calculationsGo
- Rewrote the basic synchronized forwarding code example to set both
sensors to use CSI-2 serializersGo
- Added in that VVDDIO must match VI2C
Go
- Removed the mention of 'PDB' from register 0x0DGo
- Changed BCC_Config Register[2:0] binary setting value 0b111 to
reserved.Go
- Changed PORT_CONFIG2[5] default value to 0x1Go
- Changed suggested ferrite beads for 4G FPD-Link PoC Network from
1500 kΩ to 1.5 kΩ Go
- Changed PoC network impedance recommendation from 2kΩ to
1kΩGo
- Updated the PoC descriptionGo
- Removed the insertion and return loss values from the table on
Suggested Characteristics for Single-Ended PCB Traces With Attached PoC
NetworksGo
- Added a note to explain the differences between the decoupling
capacitorsGo
- Changed the pull-up resistor for PDB from 33-kΩ to 10-kΩGo
- Changed the value of the capacitor for pin VDD11_CSI from 1-μF to 10-μF in
the diagram where VDD_SEL = HIGHGo
- Moved the additional notes in the typical application diagram from the
picture to below the diagramGo
- Added a note to clarify the power-up sequence between VDD18 and
VDDIOGo
- Removed T0 and T2 from power-up sequenceGo
- Added a note to clarify that a hard reset is optional in the
power-up sequenceGo
- Added in T7, the PDB to I2C ready delay, to the power-up
sequenceGo
- Changed the pull-up resistor for PDB from 33-kΩ to 10-kΩGo
Changes from Revision A (April 2018) to Revision B (June 2018)
- Added discrete synch signals requirement when using DVP format Go
- Changed FPD3_PCLK to fPCLK in the RAW mode line rate calculations Go
- Added information about YUV support Go
- Relaxed REFCLK Oscillator jitter specification to 200 ps maximum Go
- Relaxed REFCLK Oscillator rise and fall time to 6 ns maximum Go
- Added REFCLK spread-spectrum modulation percentage and frequency Go
- Updated Forward Channel GPIO typical latency value Go
- Updated Back Channel GPIO typical latency and jitter for 50 Mbps rate Go
- Added need for discrete synch signals in DVP mode and included RAW/YUV support Go
- Changed from GPIO7 pin to GPIO6 pin Go
- Deleted sentence "It is recommended to forward the relevant RX port data streams prior to enabling the Go
- CSI-2 TX output"Go
- Added Enabling and Disabling the CSI-2 Transmitter section Go
- Changed Node VDDIO to VI2C for SCL and SDA signal lines Go
- Added sentence about RX port specific register for registers 0x4A, 0x4B, 0x4D - 0x7F, 0xD0 - 0xDFGo
- Updated RX_PORT_STS2 register bit 1 field and description Go
- Changed PAR_ERROR line _BYTE_1 to PAR_ERROR _BYTE_1 and RX PARITY CHECKER ENABLE to RX_PARITY_CHECKER_ENABLE Go
- Redraw the PoC Network diagram Go
- Updated Return Loss S11 values Go
- Redraw RINx STP setting for figure "Typical Connection Diagram STP With
External 1.1-V supply"Go
Changes from Revision * (March 2018) to Revision A (April 2018)
- Deleted the duplicate IDD2-R1T4 parameters from the DC Electrical Characteristics tableGo
- Deleted the duplicate IDD2-R2T22 parameter from the DC Electrical Characteristics tableGo
- Deleted the duplicate IDD2-R1T22 parameter from the DC Electrical Characteristics tableGo
- Deleted the strap input current specGo
- Changed the output short circuit current symbol from ISC to IOS
Go
- Added 12-bit LF mode description and added 12-bit HF notation in the Strap Configuration Mode Select tableGo
- Changed BCC_Config Register 0x58[2:0] binary setting value from 0b100 to 0b010 to select 10 Mbps non-synchronous back channel rate.Go