ZHCSHX0C March 2018 – January 2023 DS90UB936-Q1
PRODUCTION DATA
The CSI-2 Transmitters may operate nominally at 400 or 800 Mbps, 1.5 Gbps, or 1.6 Gbps. This operation is controlled through the CSI_PLL_CTL 0x1F register (see Table 7-50). The actual CSI-2 rate is proportional to the REFCLK frequency.
| CSI_PLL_CTL[1:0] | CSI-2 TX DATA RATE PER LANE (Mbps) | REFCLK FREQUENCY (MHz) | NET CSI-2 VIDEO BANDWIDTH PER RX PORT (Gbps) |
|---|---|---|---|
| 00 | 1664 | 26 | 2.528 |
| 1600 | 25 | 2.528 | |
| 1472 | 23 | 2.528 | |
| 01 | Reserved | Reserved | Reserved |
| 10 | 800 | 25 | 1.6 (RX Port 0 and RX Port 1) |
| 11 | 400 | 25 | 0.8 (RX Port 0 and RX Port 1) |
When configuring to 800 Mbps or 1.6 Gbps, the CSI-2 timing parameters are automatically set based on the CSI_PLL_CTL 0x1F register. In the case of alternate settings, the respective CSI-2 timing parameters registers must be programmed, and the appropriate override bit must be set. For the 1.664-Gbps and 1.472-Gbps options, these settings will also affect internal device timing for back channel operation, I2C, Bidirectional Control Channel, and FrameSync operation which scale with the REFCLK frequency. Net CSI-2 video bandwidth shown for CSI-2 TX frequency of 400 Mbps and 800 Mbps in #GUID-9D63F7F3-4C25-4E9A-86D6-D1DB469E046B/X717 are for both RX ports enabled. When operating with a single RX port, the net CSI-2 video bandwidth can be up to 1.6 Gbps and 2.525 Gbps, respectively.
To operate CSI-2 at speed of 400-Mbps mode, set CSI_PLL_CTL to 11b (0x1F[1:0] =11) to enable 400-Mbps operation for the CSI-2 Transmitters. Internal PLL and Timers are then automatically adjusted for the reduced reference clock frequency. Software control of CSI-2 Transmitter timing registers is required to provide proper interface timing on the CSI-2 Output. The following are the recommended timer settings for 400-Mbps operation.
# Set CSI-2 Timing parameters
WriteI2C(0xB0,0x2) # set auto-increment, page 0
WriteI2C(0xB1,0x40) # CSI-2 Port 0
WriteI2C(0xB2,0x83) # TCK Prep
WriteI2C(0xB2,0x8D) # TCK Zero
WriteI2C(0xB2,0x87) # TCK Trail
WriteI2C(0xB2,0x87) # TCK Post
WriteI2C(0xB2,0x83) # THS Prep
WriteI2C(0xB2,0x86) # THS Zero
WriteI2C(0xB2,0x84) # THS Trail
WriteI2C(0xB2,0x86) # THS Exit
WriteI2C(0xB2,0x84) # TLPX