ZHCSHX0C March 2018 – January 2023 DS90UB936-Q1
PRODUCTION DATA
Interrupts can be brought out on the INTB pin as controlled by the INTERRUPT_CTL 0x23 and INTERRUPT_STS 0x24 registers. The main interrupt control registers provide control and status for interrupts from the individual sources. Sources include each of the two FPD-Link III Receive ports as well as the CSI-2 Transmit port. Clearing interrupt conditions requires reading the associated status register for the source. The setting of the individual interrupt status bits is not dependent on the related interrupt enable controls. The interrupt enable controls whether an interrupt is generated based on the condition, but does not prevent the interrupt status assertion.
The DS90UB936-Q1 devices have built in flexibility such that the main interrupt may be brought to any GPIO pin through the GPIOx_PIN_CTL register for that pin (see Table 7-35). Note that the GPIO3 pin is the only GPIO that is implemented as open-drain, so this is the preferred pin for signaling the interrupt.
For an interrupt to be generated based on one of the interrupt status assertions, both the individual interrupt enable and the INT_EN control must be set in the INTERRUPT_CTL 0x23 register. For example, to generate an interrupt if IS_RX0 is set, both the IE_RX0 and INT_EN bits must be set. If IE_RX0 is set but INT_EN is not, the INT status is indicated in the INTERRUPT_STS register, and the INTB pin does not indicate the interrupt condition.
See the INTERRUPT_CTL 0x23 and INTERRUPT_STS 0x24 registers for details.