ZHCSR67 July 2020 DRV8353M
PRODUCTION DATA
In the case of device latched faults, the DRV8353M family of devices goes to a partial shutdown state to help protect the external power MOSFETs and system.
When the fault condition has been removed the device can reenter the operating state by either setting the CLR_FLT SPI bit on SPI devices or issuing a result pulse to the ENABLE pin on either interface variant. The ENABLE reset pulse (tRST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the sequence should fall with the tRST time window or else the device will start the complete shutdown sequence. The reset pulse has no effect on any of the regulators, device settings, or other functional blocks