ZHCSR67 July 2020 DRV8353M
PRODUCTION DATA
The ENABLE pin manages the state of the DRV8353M family of devices. When the ENABLE pin is low, the device goes to a low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled, the VCP charge pump and VGLS regulator are disabled, the DVDD regulator is disabled, the sense amplifiers are disabled, and the SPI bus is disabled. In sleep mode all the device registers will reset to their default values. The tSLEEP time must elapse after a falling edge on the ENABLE pin before the device goes to sleep mode. The device comes out of sleep mode automatically if the ENABLE pin is pulled high. The tWAKE time must elapse before the device is ready for inputs.
In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an internal resistor.